IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 331

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Multi-Rate DFF
© June 2010 Altera Corporation
f
1
The Rate Change library contains the following blocks that allow you to control the
clock assignment to registered DSP Builder blocks, such as Delay or Increment
Decrement blocks:
■
■
■
■
■
■
For information about the
AltLab
Chapter 9, Storage
The Multi-Rate DFF block implements a D-type flipflop and typically specifies
sample rate transitions.
Simulation of the Multi-Rate DFF block may not match hardware because of
limitations in the way DSP Builder simulates multiclock designs. Typically,
differences may occur when moving from a slow to a fast clock domain. In such cases,
an error message of the following form issues in the MATLAB command window:
If your design allows, increasing the latency of the Multi-Rate DFF block to at least
one slow clock period should result in correct simulation results.
If the clocks are asynchronous, simulations do not match hardware. Do not use a
Multi-Rate DFF block to cross asynchronous clock domains, otherwise data is
corrupted or lost. Use a
transfer.
Table 7–1
Table 7–1. Multirate DFF Block Inputs and Outputs
d
q
ena
sclr
Clock
Clock_Derived
Dual-Clock FIFO
Multi-Rate DFF
PLL
Tsamp
Signal
Warning: simulation will not match hardware
Library. For information about the
shows the Multi-Rate DFF block inputs and outputs.
Input
Output
Input
Input
Library.
Direction
Dual-Clock FIFO
Clock
Preliminary
Input data port.
Output data port.
Optional clock enable port.
Optional synchronous clear port.
and
Clock_Derived
Dual-Clock FIFO
block instead to guarantee correct data
7. Rate Change Library
Description
blocks, refer to
DSP Builder Standard Blockset Libraries
block, refer to
Chapter 1,