IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 166

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

11–12
Figure 11–10. Graphical fifo_controller State Machine Diagram
DSP Builder Standard Blockset User Guide
f
12. On the Tools menu in the Quartus II State Machine Editor, click Generate HDL
For information about editing state machine properties and drawing a graphical state
machine, refer to the About the State Machine Editor topic in the Quartus II Help.
13. On the File menu in the Quartus II State Machine Editor, click Exit.
1
File to display the Generate HDL File dialog box. Select VHDL and click OK to
confirm your choice. Click Yes to save the fifo_controller.smf file and check that
there are no FSM verification errors.
1
If there are any errors, you can edit the state machine using the Properties dialog
boxes that you can display from the right button pop-up menu when you select a
state or transition. You can also edit the state machine in table format by clicking
the tabs at the bottom of the State Machine Editor window.
The fifo_controller block on your model updates with the input and output
ports defined in the state machine.
DSP Builder marks the first state that you enter in the wizard as the default
state. This state is the empty state and is the state to which the state machine
transitions when you assert the reset input.
There are five warning messages stating that FSM verification skips in each
state. You can ignore these messages.
Preliminary
Chapter 11: Using the State Machine Library
Using the State Machine Editor Block
© June 2010 Altera Corporation