IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 181

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter :
Troubleshooting Issues
The Synthesis Flow Does Not Run Properly
DSP Development Board Troubleshooting
SignalTap II Analysis Appears to Hang
Error if Output Block Connected to an Altera Synthesis Block
© June 2010 Altera Corporation
The DSP Builder automated flows allow you to control your entire synthesis and
compilation flow in the MATLAB or Simulink environment using the Signal
Compiler block. With the automated flow, the Signal Compiler block outputs
VHDL files and Tcl scripts and then automatically begins synthesis and compilation
in the Quartus II software.
If the Quartus II software does not run automatically, check the software paths and if
necessary, change the system path settings.
Check the Software Paths
If you have multiple versions of the same software product on your PC (for example,
Quartus II Web Edition and a full version of the Quartus II software), your registry
If Signal Compiler does not configure the device on the DSP development board,
check the following points:
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The SignalTap II logic analyzer should terminate successfully after it meets all trigger
conditions. However, if it does not meet one or more of the trigger conditions, the
SignalTap II analyzer does not terminate and the JTAG node remains locked.
You can either disconnect and reconnect the USB cable, or switch off the board and
switch it on again. You must program the board again if you power it off.
An Output block maps to output ports in VHDL and marks the edge of the generated
system. You should normally use these blocks to connect simulation blocks (Simulink
blocks) for your testbench. If you want to use DSP Builder blocks outside your
synthesizable system (such as for test bench generation or verification) put
Non-synthesizable Input and Non-synthesizable Output blocks around
them.
Ensure that you set up and connect the board to your PC and you install any
necessary drivers.
When the board powers up, the CONF_DONE LED illuminates. The CONF_DONE
LED turns off and then on when configuration completes successfully. If you do
not observe the LED operating in this way, configuration is unsuccessful.
You can configure the DSP board manually with an SRAM Object File (.sof), a
ByteBlasterMV, ByteBlaster II, ByteBlaster, or USB-Blaster download cable, and the
Quartus II Programmer in JTAG mode. Signal Compiler generates the SRAM
object file (.sof) file in your working directory.
Preliminary
DSP Builder Standard Blockset User Guide
13–5