MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 92
![MOD5234 10/100 ETHERNET MODULE](/photos/28/91/289101/mod-100ir_sml.jpg)
MOD5234-100IR
Manufacturer Part Number
MOD5234-100IR
Description
MOD5234 10/100 ETHERNET MODULE
Manufacturer
NetBurner Inc
Type
Controllers & Processorsr
Datasheets
1.MOD5272-100IR.pdf
(3 pages)
2.MOD5234-100IR.pdf
(4 pages)
3.MOD5234-100IR.pdf
(754 pages)
Specifications of MOD5234-100IR
Interface
I²C, SPI, UART
Voltage - Supply
2.5V
Mounting Type
Surface Mount
Package / Case
Module
Product
Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Format
-
Baud Rates
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q4483564
- Current page: 92 of 754
- Download datasheet (13Mb)
ColdFire Core
3.7.13 Fault-on-Fault Halt
If a ColdFire processor encounters any type of fault during the exception processing of another
fault, the processor immediately halts execution with the catastrophic “fault-on-fault” condition.
A reset is required to force the processor to exit this halted state.
3.7.14 Reset Exception
Asserting the reset input signal to the processor causes a reset exception. The reset exception has
the highest priority of any exception; it provides for system initialization and recovery from
catastrophic failure. Reset also aborts any processing in progress when the reset input is
recognized. Processing cannot be recovered.
The reset exception places the processor in the supervisor mode by setting the S-bit and disables
tracing by clearing the T bit in the SR. This exception also clears the M-bit and sets the processor’s
interrupt priority mask in the SR to the highest level (level 7). Next, the VBR is initialized to zero
(0x00000000). The control registers specifying the operation of any memories (e.g., cache and/or
RAM modules) connected directly to the processor are disabled.
Once the processor is granted the bus, it then performs two longword read bus cycles. The first
longword at address 0 is loaded into the stack pointer and the second longword at address 4 is
loaded into the program counter. After the initial instruction is fetched from memory, program
execution begins at the address in the PC. If an access error or address error occurs before the first
instruction is executed, the processor enters the fault-on-fault halted state.
ColdFire processors load hardware configuration information into the D0 and D1 general-purpose
registers after system reset. The hardware configuration information is loaded immediately after
the reset-in signal is negated. This allows an emulator to read out the contents of these registers
via BDM to determine the hardware configuration.
Information loaded into D0 defines the processor hardware configuration as shown in
3-16
Other implementation-specific supervisor registers are also affected.
Refer to each of the modules in this user’s manual for details on these
registers.
MCF5235 Reference Manual, Rev. 2
NOTE
Freescale Semiconductor
Figure
3-6.
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