MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 387
MOD5234-100IR
Manufacturer Part Number
MOD5234-100IR
Description
MOD5234 10/100 ETHERNET MODULE
Manufacturer
NetBurner Inc
Type
Controllers & Processorsr
Datasheets
1.MOD5272-100IR.pdf
(3 pages)
2.MOD5234-100IR.pdf
(4 pages)
3.MOD5234-100IR.pdf
(754 pages)
Specifications of MOD5234-100IR
Interface
I²C, SPI, UART
Voltage - Supply
2.5V
Mounting Type
Surface Mount
Package / Case
Module
Product
Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Format
-
Baud Rates
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q4483564
- Current page: 387 of 754
- Download datasheet (13Mb)
19.2.4.16 Descriptor Group Upper Address Register (GAUR)
The GAUR is written by the user. This register contains the upper 32 bits of the 64-bit hash table
used in the address recognition process for receive frames with a multicast address. This register
must be initialized by the user.
Freescale Semiconductor
Address
Address
Reset
Reset
Reset
Reset
31–0
Bits
W
W
W
W
R
R
R
R
—
—
Figure 19-16. Descriptor Individual Lower Address Register (IALR)
—
—
31
15
31
15
Figure 19-17. Descriptor Group Upper Address Register (GAUR)
IADDR2
Name
—
—
—
—
30
14
30
14
—
—
—
—
29
13
29
13
The lower 32 bits of the 64-bit hash table used in the address recognition process for
receive frames with a unicast address. Bit 31 of IADDR2 contains hash index bit 31. Bit 0
of IADDR2 contains hash index bit 0.
—
—
—
—
28
12
28
12
Table 19-19. IALR Field Descriptions
—
—
—
—
27
27
11
11
MCF5235 Reference Manual, Rev. 2
—
—
—
—
26
10
26
10
25
—
—
25
—
—
9
9
IPSBAR + 0x111C
IPSBAR + 0x1120
GADDR1
GADDR1
—
—
—
—
24
24
IADDR2
IADDR2
8
8
23
—
—
23
—
—
Description
7
7
—
—
—
—
22
22
6
6
—
—
—
—
21
21
5
5
—
—
—
—
20
20
4
4
Memory Map/Register Definition
—
—
—
—
19
19
3
3
—
—
—
—
18
18
2
2
—
—
—
—
17
17
1
1
16
—
—
16
—
—
0
0
19-23
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