MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 462

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

FlexCAN
21-8
Bits
31
30
29
28
27
26
25
24
23
SOFTRST Soft reset. When set, the FlexCAN resets its internal state machines (sequencer, error
NOTRDY
FRZACK
Name
SUPV
MDIS
HALT
FRZ
—
—
Module disable. This bit controls whether FlexCAN is enabled or not. When disabled,
FlexCAN shuts down the FlexCAN clocks that drive the CAN interface and Message Buffer
sub-module. This is the only bit in CANMCRn not affected by soft reset. See
Section 21.1.3.3, “Module Disabled
0 Enable the FlexCAN module, clocks enabled
1 Disable the FlexCAN module, clocks disabled
Freeze mode enable. When set, the FlexCAN can enter freeze mode when the BKPT line
is asserted or the HALT bit is set. Clearing this bit causes the FlexCAN to exit freeze mode.
Refer to
0 FlexCAN ignores the BKPT signal and the CANMCRn[HALT] bit.
1 FlexCAN module enabled to enter debug mode.
Reserved, should be cleared.
Halt FlexCAN. Setting this bit puts the FlexCAN module into freeze mode. It has the same
effect as assertion of the BKPT signal. This bit is set after reset and should be cleared after
initializing the message buffers and control registers. FlexCAN message buffer receive
and transmit functions are inactive until this bit is cleared. While in freeze mode, the CPU
has write access to the error counter register (ERRCNTn), that is otherwise read-only.
0 The FlexCAN operates normally
1 FlexCAN enters freeze mode if FRZ = 1
FlexCAN not ready. This bit indicates that the FlexCAN is either in disable or freeze mode.
This bit is read-only and it is cleared once the FlexCAN exits these modes.
0 FlexCAN is either in normal mode, listen-only mode, or loop-back mode.
h1FlexCAN is in disable or freeze mode.
Reserved, should be cleared.
counters, error flags, and timer) and the host interface registers (CANMCRn [except the
MDIS bit], TIMER, ERRCNT, ERRSTAT, IMASK, and IFLAG).
The configuration registers that control the interface with the CAN bus are not changed
(CANCTRLn, RXGMASKn, RX14MASKn, RX15MASKn). Message buffers are also not
changed. This allows SOFTRST to be used as a debug feature while the system is running.
Since soft reset is synchronous and has to follow a request/acknowledge procedure across
clock domains, it may take some time to fully propagate its effect. The SOFTRST bit
remains set while reset is pending and is automatically cleared when reset completes. The
user should poll this bit to know when the soft reset has completed.
0 Soft reset cycle completed
1 Soft reset cycle initiated
Freeze acknowlege. Indicates that the FlexCAN module has entered freeze mode. The
user should poll this bit after freeze mode has been requested, to know when the module
has actually entered freeze mode. When freeze mode is exited, this bit is cleared once the
FlexCAN prescaler is enabled. This is a read-only bit.
0 The FlexCAN has exited freeze mode and the prescaler is enabled.
1 The FlexCAN has entered freeze mode, and the prescaler is disabled.
Supervisor/user data space. Places the FlexCAN registers in either supervisor or user data
space.
0 Registers with access controlled by the SUPV bit are accessible in either user or
1 Registers with access controlled by the SUPV bit are restricted to supervisor mode.
Table 21-2. CANMCRn Field Descriptions
supervisor privilege mode.
Section 21.1.3.2, “Freeze
MCF5235 Reference Manual, Rev. 2
Mode” for more information.
Mode” for more information.
Description
Freescale Semiconductor