MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 664

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Debug Support
CSR[27–24] indicates the halt source, showing the highest priority source for multiple halt
conditions.
32.5.2
When the CPU is halted and PST reflects the halt status, the development system can send
unrestricted commands to the debug module. The debug module implements a synchronous
protocol using two inputs (DSCLK and DSI) and one output (DSO), where DSO is specified as a
delay relative to the rising edge of the processor clock. See
serves as the serial communication channel master and must generate DSCLK.
The serial channel operates at a frequency from DC to 1/5 of the PSTCLK frequency. The channel
uses full-duplex mode, where data is sent and received simultaneously by both master and slave
devices. The transmission consists of 17-bit packets composed of a status/control bit and a 16-bit
data word. As shown in
when DSCLK is high; that is, DSI is sampled and DSO is driven.
DSCLK and DSI are synchronized inputs. DSCLK acts as a pseudo clock enable and is sampled
on the rising edge of the processor clock as well as the DSI. DSO is delayed from the
DSCLK-enabled CLK rising edge (registered after a BDM state machine state change). All events
in the debug module’s serial state machine are based on the processor clock rising edge. DSCLK
must also be sampled low (on a positive edge of CLK) between each bit exchange. The MSB is
32-20
• The ColdFire architecture also handles a special case of BKPT being asserted while the
control to the instruction address in the PC, bypassing normal reset exception processing.
If the PC was not loaded, the
continue reset exception processing.
processor is stopped by execution of the STOP instruction. For this case, the processor exits
the stopped mode and enters the halted state, at which point, all BDM commands may be
exercised. When restarted, the processor continues by executing the next sequential
instruction, that is, the instruction following the STOP opcode.
BDM State
PSTCLK
Machine
DSCLK
BDM Serial Interface
DSO
DSI
Figure
Figure 32-12. BDM Serial Interface Timing
Current State
32-12, all state transitions are enabled on a rising edge of PSTCLK
Past
MCF5235 Reference Manual, Rev. 2
GO
C1
Current
command causes the processor to exit halted state and
C2
C3
C4
Table
32-1. The development system
Next State
Current
Next
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