MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 650

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Debug Support
Another example of a variant branch instruction would be a JMP (A0) instruction.
shows the PST and DDATA outputs that indicate a JMP (A0) execution (assuming the CSR was
programmed to display the lower 2 bytes of an address).
PST 0x5 indicates a taken branch and the marker value 0x9 indicates a 2-byte address. Thus, the
subsequent 4 nibbles of DDATA display the lower 2 bytes of address register A0 in
least-to-most-significant nibble order. The PST output after the JMP instruction completes
depends on the target instruction. The PST can continue with the next instruction before the
address has completely displayed on DDATA because of the DDATA FIFO. If the FIFO is full and
the next instruction has captured values to display on DDATA, the pipeline stalls (PST = 0x0) until
space is available in the FIFO.
32.4
In addition to the existing BDM commands that provide access to the processor’s registers and the
memory subsystem, the ColdFire debug module contains ten registers to support the required
functionality. These registers are also accessible from the processor’s supervisor programming
model by executing the WDEBUG instruction (write only). Thus, the breakpoint hardware in the
debug module can be written by the external development system using the debug serial interface
or by the operating system running on the processor core. Software is responsible for guaranteeing
that accesses to these resources are serialized and logically consistent. Hardware provides a
locking mechanism in the CSR to allow the external development system to disable any attempted
writes by the processor to the breakpoint registers (setting CSR[IPW]). BDM commands must not
be issued if the MCF5235 is using the WDEBUG instruction to access debug module registers or
the resulting behavior is undefined.
These registers, shown in
implemented bits.
32-6
PSTCLK
DDATA
DRc[4–0]
PST
Memory Map/Register Definition
0x00
Figure 32-3. Example JMP Instruction Output on PST/DDATA
Configuration/status register
Table 32-3. ColdFire Core Debug Programming Model
0x5
0x0
Table
Register Name
32-3, are treated as 32-bit quantities, regardless of the number of
0x9
0x0
MCF5235 Reference Manual, Rev. 2
default
A[3:0]
default
A[7:4]
Abbreviation
CSR
A[11:8]
default
0x0000_0000
Initial State
A[15:12]
default
Freescale Semiconductor
p. 32-10
Page
Figure 32-3