MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 136

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Cache
Table 5-5
configuration.
Table 5-6
cache invalidate all bit.
5.2.1.2
The ACRs provide a definition of memory reference attributes for two memory regions (one per
ACR). This set of effective attributes is defined for every memory reference using the ACRs or
the set of default attributes contained in the CACR. The ACRs are examined for every processor
memory reference that is not mapped to the SRAM memories.
The ACRs are 32-bit write-only supervisor control register. They are accessed in the CPU address
space via the MOVEC instruction with an Rc encoding of 0x004 and 0x005. The ACRs can be
read when in background debug mode (BDM). At system reset, both registers are cleared.
5-10
[CENB]
CACR
CACR
[DISI]
shows the relationship between CACR bits DISI, DISD, INVI, & INVD and setting the
shows the relationship between CACR bits CENB, DISI, & DISD and the cache
0
1
1
1
0
0
0
0
1
0
Access Control Registers (ACR0, ACR1)
[DISD]
CACR
CACR
[DISI]
0
0
1
0
0
0
0
0
1
x
Table 5-5. Cache Configuration as Defined by CACR
Table 5-6. Cache Invalidate All as Defined by CACR
[DISD]
CACR
CACR
[INVI]
0
1
0
0
0
1
1
x
x
x
[INVD]
CACR
Instruction Cache
Split Instruction/
Configuration
MCF5235 Reference Manual, Rev. 2
0
1
0
1
x
x
Data Cache
Data Cache
N/A
Split Instruction/
Data Cache
Split Instruction/
Data Cache
Split Instruction
Data Cache
Split Instruction/
Data Cache
Instruction Cache
Data Cache
Configuration
Cache is completely disabled
4 KByte direct-mapped instruction cache (uses lower
half of tag and storage arrays) and 4 KByte
direct-mapped write-through data cache (uses upper
half of tag and storage arrays)
8 KByte direct-mapped instruction cache (uses all of
tag and storage arrays)
8 KByte direct-mapped write-through data cache
(uses all of tag and storage arrays)
Invalidate 8 KByte instruction cache
Invalidate all entries in both 4 KByte
instruction cache and 4 KByte data cache
Invalidate only 4 KByte data cache
Invalidate only 4 KByte instruction cache
No invalidate
Invalidate 8 KByte data cache
Description
Operation
Freescale Semiconductor