MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 747

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Program counter 3-3
Q
QSPI
R
Registers
Freescale Semiconductor
registers
baud rate 25-6
memory map 25-9
operation
programming example 25-16
RAM
registers
Rx
signals 25-2
Tx
cache
CCM
chip select module
clock module
core
low-power control (LPCR) 8-3
low-power interrupt control (LPICR) 8-2
low-power modes 8-8
master mode 25-3
command 25-6
model 25-4
receive 25-5
transmit 25-5
address (QAR) 25-14
command RAM (QCRn) 25-14
data (QDR) 25-14
delay (QDLYR) 25-11
interrupt (QIR) 25-12
mode (QMR) 25-9
wrap (QWR) 25-12
RAM 25-5
delays 25-7
length 25-8
RAM 25-5
access control 0–1 (ACRn) 3-8
control (CACR) 3-7
chip configuration (CCR) 9-4
chip identification (CIR) 9-7
reset configuration (RCON) 9-5
address (CSARn) 16-7
control (CSCRn) 16-9
mask (CSMRn) 16-8
synthesizer control (SYNCR) 7-8
synthesizer status (SYNSR) 7-11
address (An) 3-3
,
5-7
,
5-10
MCF5235 Reference Manual, Rev. 2
debug
DMA controller
EMAC
EPORT
Ethernet
condition code (CCR) 3-4
data (Dn) 3-2
program counter (PC) 3-3
stack pointer (A7) 3-3
status register (SR) 3-6
vector base (VBR) 3-7
address attribute trigger (AATR) 32-8
address breakpoint (ABLR, ABHR) 32-9
configuration/status (CSR) 32-10
data breakpoint/mask (DBR, DBMR) 32-15
program counter breakpoint/mask
trigger definition (TDR) 32-17
byte count (BCRn) 14-7
control (DCRn) 14-9
destination address (DARn) 14-7
request control (DMAREQC) 14-5
source address (SARn) 14-6
status (DSRn) 14-8
mask (MASK) 4-11
status (MACSR) 4-6
data direction (EPDDR) 15-4
flag (EPFR) 15-6
pin assignment (EPPAR) 15-3
pin data (EPPDR) 15-6
port data (EPDR) 15-5
port interrupt enable (EPIER) 15-5
control (ECR) 19-13
descriptor group upper/lower address
descriptor individual upper/lower
descriptor individual upper/lower address
FIFO receive bound (FRBR) 19-25
FIFO receive start (FRSR) 19-26
FIFO transmit FIFO watermark (TFWR) 19-25
interrupt event (EIR) 19-9
interrupt mask (EIMR) 19-10
MIB control (MIBC) 19-17
MII management frame (MMFR) 19-14
MII speed control (MSCR) 19-16
opcode/pause duration (OPD) 19-21
physical address low (PALRn) 19-20
physical address low/high (PALR, PAUR) 19-20
receive buffer size (EMRBR) 19-28
receive control (RCR) 19-18
(PBR/PBMR) 32-16
(GAUR/GALR) 19-24
(IAUR/IALR) 19-23
(IAUR/IALR) 19-22
,
3-7
Index-7