MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 268

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Interrupt Controller Modules
13.1.2.3 Interrupt Vector Determination
Once the core has sampled for pending interrupts and begun interrupt exception processing, it
generates an interrupt acknowledge cycle (IACK). The IACK transfer is treated as a
memory-mapped byte read by the processor, and routed to the appropriate interrupt controller.
Next, the interrupt controller extracts the level being acknowledged from address bits[4:2], and
then determines the highest priority interrupt request active for that level, and returns the 8-bit
interrupt vector for that request to complete the cycle. The 8-bit interrupt vector is formed using
the following algorithm:
For INTC0,
For INTC1,
Recall vector_numbers 0 - 63 are reserved for the ColdFire processor and its internal exceptions.
Thus, the following mapping of bit positions to vector numbers applies for the INTC0:
if interrupt source 1 is active and acknowledged,then vector_number =
if interrupt source 2 is active and acknowledged,then vector_number =
...
if interrupt source 8 is active and acknowledged,then vector_number =
if interrupt source 9 is active and acknowledged,then vector_number =
...
if interrupt source 62 is active and acknowledged,then vector_number = 126
The net effect is a fixed mapping between the bit position within the source to the actual interrupt
vector number.
If there is no active interrupt source for the given level, a special “spurious interrupt” vector
(vector_number = 24) is returned and it is the responsibility of the service routine to handle this
error situation.
Note this protocol implies the interrupting peripheral is not accessed during the acknowledge cycle
since the interrupt controller completely services the acknowledge. This means the interrupt
source must be explicitly disabled in the interrupt service routine. This design provides unique
vector capability for all interrupt requests, regardless of the “complexity” of the peripheral device.
13.2
The register programming model for the interrupt controllers is memory-mapped to a 256-byte
space. In the following discussion, there are a number of program-visible registers greater than 32
bits in size. For these control fields, the physical register is partitioned into two 32-bit values: a
register “high” (the upper longword) and a register “low” (the lower longword). The nomenclature
<reg_name>H and <reg_name>L is used to reference these values.
13-4
Memory Map/Register Definition
vector_number = 64 + interrupt source number
vector_number = 128 + interrupt source number
MCF5235 Reference Manual, Rev. 2
Freescale Semiconductor
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