MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 541

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Freescale Semiconductor
Bits
7
6
5
4
3
2
1
0
RxRDY
TxEMP
TxRDY
FFULL
Name
RB
OE
FE
PE
Received break. The received break circuit detects breaks that originate in the middle of a
received character. However, a break in the middle of a character must persist until the end
of the next detected character time.
0 No break was received.
1 An all-zero character of the programmed length was received without a stop bit. Only a
Framing error.
0 No framing error occurred.
1 No stop bit was detected when the corresponding data character in the FIFO was
Parity error. Valid only if RxRDY = 1.
0 No parity error occurred.
1 If UMR1n[PM] = 0x (with parity or force parity), the corresponding character in the FIFO
Overrun error. Indicates whether an overrun occurs.
0 No overrun occurred.
1 One or more characters in the received data stream have been lost. OE is set upon
Transmitter empty.
0 The transmit buffer is not empty. Either a character is being shifted out, or the transmitter
1 The transmitter has underrun (both the transmitter holding register and transmitter shift
Transmitter ready.
0 The CPU loaded the transmitter holding register or the transmitter is disabled.
1 The transmitter holding register is empty and ready for a character. TxRDY is set when
FIFO full.
0 The FIFO is not full but may hold up to two unread characters.
1 A character was received and the receiver FIFO is now full. Any characters received
Receiver ready.
0 The CPU has read the receive buffer and no characters remain in the FIFO after this
1 One or more characters were received and are waiting in the receive buffer FIFO.
single FIFO position is occupied when a break is received. Further entries to the FIFO
are inhibited until UnRXD returns to the high state for at least one-half bit time, which is
equal to two successive edges of the UART clock. RB is valid only when RxRDY = 1.
received. The stop-bit check occurs in the middle of the first stop-bit position. FE is valid
only when RxRDY = 1.
was received with incorrect parity. If UMR1n[PM] = 11 (multidrop), PE stores the
received address or data (A/D) bit. PE is valid only when RxRDY = 1.
receipt of a new character when the FIFO is full and a character is already in the shift
register waiting for an empty FIFO position. When this occurs, the character in the
receiver shift register and its break detect, framing error status, and parity error, if any,
are lost. OE is cleared by the
is disabled. The transmitter is enabled/disabled by programming UCRn[TC].
registers are empty). This bit is set after transmission of the last stop bit of a character
if there are no characters in the transmitter holding register awaiting transmission.
a character is sent to the transmitter shift register or when the transmitter is first enabled.
If the transmitter is disabled, characters loaded into the transmitter holding register are
not sent.
when the FIFO is full are lost.
read.
Table 26-5. USRn Field Descriptions
MCF5235 Reference Manual, Rev. 2
RESET ERROR STATUS
Description
command in UCRn.
Memory Map/Register Definition
26-9