MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 560

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

UART Modules
26.4.6.1 Interrupt and DMA Request Initialization
26.4.6.1.1 Setting up the UART to Generate Core Interrupts
The list below gives the steps needed to properly initialize the UART to generate an interrupt
request to the core.
26.4.6.1.2 Setting up the UART to Request DMA Service
The UART is capable of generating two different DMA request signals–transmit DMA requests
and receive DMA requests.
The transmit DMA request signal is asserted when the TxRDY (transmitter ready) in the UART
Interrupt Status Register, UISRn[TxRDY], is set. When the transmit DMA request signal is
asserted, the DMA can initiate a data copy, reading the next character to be transmitted from
memory and writing it into the UART transmit buffer (UTBn). This would allow the DMA channel
to stream data from memory to the UART for transmission without processor intervention. Once
the entire message has been moved into the UART, the DMA would typically generate an
end-of-data-transfer interrupt request to the CPU. The resulting interrupt service routine (ISR)
could query the UART programming model to determine the end-of-transmission status.
26-28
1. Initialize ICRx register in the interrupt controller (ICR13 for UART0, ICR14 for UART1,
2. Unmask appropriate bits in IMR in the interrupt controller (bits 13-15 for UART0-UART2
3. Unmask appopriate bits in the core’s Status Register (SR) to enable interrupts.
4. If TxRDY or RxRDY are being used to generate interrupt requests, then verify that
5. Initialize interrupts in the UART, see
SIRQ then clears the interrupt source, waits for the next change-in-break interrupt (end of
break), clears the interrupt source again, then returns from exception processing to the
system monitor.
and ICR15 for UART2).
respectively).
DMAREQC (in the SCM) does not also assign the UART’s TxRDYand RxRDY into
DMA channels.
Register
UMR1x
UIMRx
UIMRx
UIMRx
UIMRx
Table 26-13. UART Interrupts
MCF5235 Reference Manual, Rev. 2
Bit
6
7
2
1
0
Table
RxIRQ
Change of State (COS)
Delta Break
RxFIFO Full
TxRDY
26-13.
Interrupt
Freescale Semiconductor