MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 394

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Fast Ethernet Controller (FEC)
before the DMA begins. If the TxBDs are set up in order, the DMA Controller could DMA the first
BD before the 2nd was made available, potentially causing a transmit FIFO underrun.
In the FEC, the DMA is notified by the driver that new transmit frame(s) are available by writing
to the TDAR register. When this register is written to (data value is not significant) the FEC RISC
will tell the DMA to read the next transmit BD in the ring. Once started, the RISC + DMA will
continue to read and interpret transmit BDs in order and DMA the associated buffers, until a
transmit BD is encountered with the R bit = 0. At this point the FEC will poll this BD one more
time. If the R bit = 0 the second time, then the RISC will stop the transmit descriptor read process
until software sets up another transmit frame and writes to TDAR.
When the DMA of each transmit buffer is complete, the DMA writes back to the BD to clear the
R bit, indicating that the hardware consumer is finished with the buffer.
19.2.5.1.2 Driver/DMA Operation with Receive BDs
Unlike transmit, the length of the receive frame is unknown by the driver ahead of time. Therefore
the driver must set a variable to define the length of all receive buffers. In the FEC, this variable
is written to the EMRBR register.
The driver (RxBD software producer) should set up some number of “empty” buffers for the
Ethernet by initializing the address field and the E and W bits of the associated receive BDs. The
hardware (receive DMA) will consume these buffers by filling them with data as frames are
received and clearing the E bit and writing to the L (1 indicates last buffer in frame) bit, the frame
status bits (if L = 1) and the length field.
If a receive frame spans multiple receive buffers, the L bit is only set for the last buffer in the
frame. For non-last buffers, the length field in the receive BD will be written by the DMA (at the
same time the E bit is cleared) with the default receive buffer length value. For end of frame buffers
the receive BD will be written with L = 1 and information written to the status bits (M, BC, MC,
LG, NO, CR, OV, TR). Some of the status bits are error indicators which, if set, indicate the receive
frame should be discarded and not given to higher layers. The frame status/length information is
written into the receive FIFO following the end of the frame (as a single 32-bit word) by the
receive logic. The length field for the end of frame buffer will be written with the length of the
entire frame, not just the length of the last buffer.
For simplicity the driver may assign the default receive buffer length to be large enough to contain
an entire frame, keeping in mind that a malfunction on the network or out of spec implementation
could result in giant frames. Frames of 2k (2048) bytes or larger are truncated by the FEC at 2032
bytes so software is guaranteed never to see a receive frame larger than 2032 bytes.
Similar to transmit, the FEC will poll the receive descriptor ring after the driver sets up receive
BDs and writes to the RDAR register. As frames are received the FEC will fill receive buffers and
update the associated BDs, then read the next BD in the receive descriptor ring. If the FEC reads
MCF5235 Reference Manual, Rev. 2
19-30
Freescale Semiconductor