MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 362

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Synchronous DRAM Controller Module
18.4.5 Mode Register Initialization
When DACR[IMRS] is set, a bus cycle initializes the mode register. If the mode register setting is
read on A[10:0] of the SDRAM on the first bus cycle, the bit settings on the corresponding
MCF5235 address pins must be determined while being aware of masking requirements.
Table 18-30
Next, this information is mapped to an address to determine the hexadecimal value.
Although A[31:20] corresponds to the address programmed in DACR0, according to how DACR0
and DMR0 are initialized, bit 19 must be set to hit in the SDRAM. Thus, before the mode register
bit is set, DMR0[19] must be set to enable masking.
18-24
Setting
Setting
(hex)
(hex)
Field
Field
lists the desired initialization setting:
31
15
0
x
Table 18-31. Mode Register Mapping to MCF5235 A[31:0]
30
14
x
0
MCF5235 Pins
0
0
29
13
x
0
A20
A19
A18
A17
A10
A11
A12
A13
A14
A15
A9
Table 18-30. Mode Register Initialization
28
12
x
0
27
11
1
x
MCF5235 Reference Manual, Rev. 2
SDRAM Pins
26
10
0
x
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
8
25
x
0
9
24
x
x
8
Mode Register Initialization
Reserved
Opmode
Opmode
CASL
CASL
CASL
23
x
x
7
WB
BT
BL
BL
BL
22
x
6
x
0
0
21
x
5
x
20
x
x
4
X
0
0
0
0
0
1
0
0
0
0
19
0
x
3
Freescale Semiconductor
18
0
2
x
0
0
17
0
1
x
16
V
x
0
x