MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 547

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

26.3.11 UART Baud Rate Generator Registers (UBG1n/UBG2n)
The UBG1n registers hold the msb, and the UBG2n registers hold the lsb of the preload value.
UBG1n and UBG2n concatenate to provide a divider to the internal bus clock for
transmitter/receiver operation, as described in
Rates.”
Freescale Semiconductor
Bits
6–3
7
2
1
0
Figure 26-13. UART Baud Rate Generator Register (UBG1n)
FFULL/
RxRDY
TxRDY
Name
COS
Address
DB
—
Reset
W
R
Table 26-10. UISRn/UIMRn Field Descriptions
Change-of-state.
0 UIPCRn[COS] is not selected.
1 Change-of-state occurred on UnCTS and was programmed in UACRn[IEC] to cause an
Reserved, should be cleared.
Delta break.
0 No new break-change condition to report.
1 The receiver detected the beginning or end of a received break.
Status of FIFO or receiver, depending on UMR1[FFULL/RxRDY] bit. Duplicate of
USRn[FIFO] & USRn[RxRDY]
Transmitter ready. This bit is the duplication of USRn[TxRDY].
0 The transmitter holding register was loaded by the CPU or the transmitter is disabled.
1 The transmitter holding register is empty and ready to be loaded with a character.
interrupt.
(UCRn),” describes the
Characters loaded into the transmitter holding register when TxRDY = 0 are not sent.
0
7
[FFULL/RxRDY
IPSBAR + 0x0218 (UBG10); IPSBAR + 0x0258 (UBG11);
UIMRn
0
1
0
1
]
MCF5235 Reference Manual, Rev. 2
0
6
0
[FFULL/RxRDY]
5
IPSBAR + 0x0298 (UBG12)
RESET BREAK
UISRn
0
0
1
1
Divider MSB
0
4
Section 26.4.1.2.1, “internal Bus Clock Baud
Description
-
0
3
CHANGE INTERRUPT
Receiver not ready
Receiver not ready
Receiver is ready,
Receiver is ready,
Do not interrupt
Section 26.3.5, “UART Command Registers
0 (RxRDY)
interrupt
2
0
UMR1n[FFULL/RxRDY]
0
1
command.
Memory Map/Register Definition
0
0
Do not interrupt
FIFO not full
FIFO not full
FIFO is full,
FIFO is full,
1 (FIFO)
interrupt
26-15