MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 426

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Enhanced Time Processing Unit (eTPU)
20.4
The eTPU is capable of working in the following modes:
These modes are loosely selected: there is no unique register field or signals to choose between
them. Some features of one mode can be used with features of other mode(s).
20.4.1 eTPU Mode Selection
User and user configuration are the production operating modes, and differ from each other only
in access to SCM. The SCM can either be accessed directly from the internal bus for code loading,
or for software breakpoint setting.
Module disable mode is entered by setting the ETPU_ECR[MDIS] bit.
20-12
• User configuration mode
• User mode
• Debug mode
• Module Disable Mode
— By having access to the shared code memory (SCM), the core has the ability to program
— The core does not access the eTPU shared code memory.
— Use of pre-defined eTPU functions.
eTPU debug support is provided by special Trace/Debug features accessed via the
integrated debug module (see
— hardware breakpoint/watchpoint setting
— access to internal registers
— single-step execution
— forced instruction execution
— software breakpoint insertion and removal.
eTPU engine clocks are stopped through a register write to the ETPU_ECR[MDIS] bit
saving power. Input sampling stops and TCR1 and TCR2 stop incrementing. Only the
engine clock is stopped, the shared BIU and global channel registers can be accessed and
interrupts can be cleared, enabled, or disabled. The eTPU only enters STOP mode after
completion of the current thread.
Modes of Operation
the eTPU cores with time functions.
Data transfer requests are implemented as a single DMA request to the
MCF5235’s DMA controller. All 32 channels’ data transfer request
signals are logically OR’d to produce this single DMA request.
MCF5235 Reference Manual, Rev. 2
Chapter 32, “Debug
NOTE
Support” for more details):
Freescale Semiconductor