MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 374

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Fast Ethernet Controller (FEC)
19.2.4.2 Interrupt Mask Register (EIMR)
The EIMR register controls which interrupt events are allowed to generate actual interrupts. All
implemented bits in this CSR are read/write. This register is cleared upon a hardware reset. If the
corresponding bits in both the EIR and EIMR registers are set, the interrupt will be signalled to the
CPU. The interrupt signal will remain asserted until a 1 is written to the EIR bit (write 1 to clear)
or a 0 is written to the EIMR bit.
19-10
18–0
Bits
29
28
27
26
25
24
23
22
21
20
19
EBERR
Name
BABT
GRA
RXF
RXB
TXF
TXB
MII
UN
LC
RL
—
Table 19-4. EIR Field Descriptions (Continued)
Babbling transmit error. This bit indicates that the transmitted frame length has exceeded
RCR[MAX_FL] bytes. This condition is usually caused by a frame that is too long being
placed into the transmit data buffer(s). Truncation does not occur.
Graceful stop complete. This interrupt will be asserted for one of three reasons. Graceful
stop means that the transmitter is put into a pause state after completion of the frame
currently being transmitted.
1) A graceful stop, which was initiated by the setting of the TCR[GTS] bit is now complete.
2) A graceful stop, which was initiated by the setting of the TCR[TFC_PAUSE] bit is now
3) A graceful stop, which was initiated by the reception of a valid full duplex flow control
Transmit frame interrupt. This bit indicates that a frame has been transmitted and that the
last corresponding buffer descriptor has been updated.
Transmit buffer interrupt. This bit indicates that a transmit buffer descriptor has been
updated.
Receive frame interrupt. This bit indicates that a frame has been received and that the last
corresponding buffer descriptor has been updated.
Receive buffer interrupt. This bit indicates that a receive buffer descriptor has been
updated that was not the last in the frame.
MII interrupt. This bit indicates that the MII has completed the data transfer requested.
Ethernet bus error. This bit indicates that a system bus error occurred when a DMA
transaction was underway. When the EBERR bit is set, ECR[ETHER_EN] will be cleared,
halting frame processing by the FEC. When this occurs software will need to insure that
the FIFO controller and DMA are also soft reset.
Late collision. This bit indicates that a collision occurred beyond the collision window (slot
time) in half duplex mode. The frame is truncated with a bad CRC and the remainder of the
frame is discarded.
Collision retry limit. This bit indicates that a collision occurred on each of 16 successive
attempts to transmit the frame. The frame is discarded without being transmitted and
transmission of the next frame will commence. Can only occur in half duplex mode.
Transmit FIFO underrun. This bit indicates that the transmit FIFO became empty before
the complete frame was transmitted. A bad CRC is appended to the frame fragment and
the remainder of the frame is discarded.
Reserved, should be cleared.
complete.
“pause” frame is now complete. Refer to
MCF5235 Reference Manual, Rev. 2
Description
Section 19.3.10, “ Full Duplex Flow Control.”
Freescale Semiconductor