MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 266

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Interrupt Controller Modules
During the interrupt exception processing, the CPU enters supervisor mode, disables trace mode
and then fetches an 8-bit vector from the interrupt controller. This byte-sized operand fetch is
known as the interrupt acknowledge (IACK) cycle with the ColdFire implementation using a
special encoding of the transfer type and transfer modifier attributes to distinguish this data fetch
from a “normal” memory access. The fetched data provides an index into the exception vector
table which contains 256 addresses, each pointing to the beginning of a specific exception service
routine. In particular, vectors 64 - 255 of the exception vector table are reserved for user interrupt
service routines. The first 64 exception vectors are reserved for the processor to handle reset, error
conditions (access, address), arithmetic faults, system calls, etc. Once the interrupt vector number
has been retrieved, the processor continues by creating a stack frame in memory. For ColdFire, all
exception stack frames are 2 longwords in length, and contain 32 bits of vector and status register
data, along with the 32-bit program counter value of the instruction that was interrupted (see
Section 3.6, “Exception Stack Frame
Definition” for more information on the stack frame format).
After the exception stack frame is stored in memory, the processor accesses the 32-bit pointer from
the exception vector table using the vector number as the offset, and then jumps to that address to
begin execution of the service routine. After the status register is stored in the exception stack
frame, the SR[I] mask field is set to the level of the interrupt being acknowledged, effectively
masking that level and all lower values while in the service routine. For many peripheral devices,
the processing of the IACK cycle directly negates the interrupt request, while other devices require
that request to be explicitly negated during the processing of the service routine.
For the MCF5235, the processing of the interrupt acknowledge cycle is fundamentally different
than previous 68K/ColdFire cores. In the new approach, all IACK cycles are directly handled by
the interrupt controller, so the requesting peripheral device is not accessed during the IACK. As a
result, the interrupt request must be explicitly cleared in the peripheral during the interrupt service
routine. For more information, see
Section 13.1.2.3, “Interrupt Vector
Determination.”
Unlike the M68000 family, all ColdFire processors guarantee that the first instruction of the
service routine is executed before sampling for interrupts is resumed. By making this initial
instruction a load of the SR, interrupts can be safely disabled, if required.
During the execution of the service routine, the appropriate actions must be performed on the
peripheral to negate the interrupt request.
For more information on exception processing, see the ColdFire Programmer’s Reference Manual
at http://www.freescale.com/coldfire.
13.1.2 Interrupt Controller Theory of Operation
To support the interrupt architecture of the 68K/ColdFire programming model, the combined 63
interrupt sources are organized as 7 levels, with each level supporting up to 9 prioritized requests.
Consider the priority structure within a single interrupt level (from highest to lowest priority) as
shown in
Table
13-1.
MCF5235 Reference Manual, Rev. 2
13-2
Freescale Semiconductor