MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 529

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Figure 25-10
Freescale Semiconductor
Address
Reset
11–8
Bits
7–0
15
14
13
12
W CONT BITSE
R
—
15
shows the command RAM register.
The command RAM is accessed only using the most significant byte
of QDR and indirect addressing based on QAR[ADDR].
In order to keep the chip selects asserted for all transfers, the
QWR[CSIV] bit must be set to control the level that the chip selects
return to after the first transfer.
QSPI_CS
CONT
BITSE
Name
DSCK
14
—
DT
Figure 25-10. Command RAM Registers (QCR0–QCR15)
—
DT
13
—
Table 25-8. QCR0–QCR15 Field Descriptions
Continuous.
0 Chip selects return to inactive level defined by QWR[CSIV] when transfer is complete.
1 Chip selects remain asserted after the transfer of 16 words of data (see note below).
Bits per transfer enable.
0 Eight bits
1 Number of bits set in QMR[BITS]
Delay after transfer enable.
0 Default reset value.
1 The QSPI provides a variable delay at the end of serial transfer to facilitate interfacing
Chip select to QSPI_CLK delay enable.
0 Chip select valid to QSPI_CLK transition is one-half QSPI_CLK period.
1 QDLYR[QCD] specifies the delay from QSPI_CS valid to QSPI_CLK.
Peripheral chip selects. Used to select an external device for serial data transfer. More than
one chip select may be active at once, and more than one device can be connected to each
chip select. Bits 11–8 map directly to QSPI_CS[3:0], respectively. If it is desired to use
those bits as a chip select value, then an external demultiplexor must be connected to the
QSPI_CS[3:0] pins.
Reserved, should be cleared.
with peripherals that have a latency requirement. The delay between transfers is
determined by QDLYR[DTL].
DSCK
—
12
—
11
MCF5235 Reference Manual, Rev. 2
QSPI_CS
—
10
—
9
NOTE
NOTE
QAR[ADDR]
—
8
Description
—
0
7
—
0
6
—
0
5
—
0
4
Memory Map/Register Definition
—
0
3
—
2
0
—
0
1
—
0
0
25-15