MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 647

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Freescale Semiconductor
32.2
Table 32-1
unidirectional and related to a rising edge of the processor’s clock signal. The standard
26-pin debug connector is shown in
Figure 32-2
32.3
Real-time trace, which defines the dynamic execution path, is a fundamental debug
function. The ColdFire solution is to include a parallel output port providing encoded
processor status and data to an external development system. This port is partitioned into
Signal Name
DDATA[3:0]
PSTCLK
PST[3:0]
DSCLK
BKPT
DSO
DSI
PST
External Signal Description
Real-Time Trace Support
PSTCLK
or
shows PSTCLK timing with respect to PST and DDATA.
describes the debug module signals. All ColdFire debug signals are
DDATA
Development Serial
Development Serial
Development Serial
Processor Status
Processor Status
Debug Data
Breakpoint
Signal
Output
Clock
Clock
Input
Table 32-1. Debug Module Signals
Figure 32-2. PSTCLK Timing
See
sample PST and DDATA values.
Internally synchronized input. (The logic level on DSCLK is validated if it has
the same value on two consecutive rising PSTCLK edges.) Clocks the serial
communication port to the debug module during packet transfers. Maximum
frequency is 1/5 the processor status clock (PSTCLK) speed. At the
synchronized rising edge of DSCLK, the data input on DSI is sampled and
DSO changes state.
Internally synchronized input that provides data input for the serial
communication port to the debug module.
Provides serial output communication for debug module responses. DSO is
registered internally.
Input used to request a manual breakpoint. Assertion of BKPT puts the
processor into a halted state after the current instruction completes. Halt
status is reflected on processor status signals (PST[3:0]) as the value 0xF.
These output signals display the register breakpoint status as a default, or
optionally, captured address and operand values. The capturing of data
values is controlled by the setting of the CSR. Additionally, execution of the
WDDATA instruction by the processor captures operands which are displayed
on DDATA. These signals are updated each processor cycle.
These output signals report the processor status.
encoding of these signals. These outputs indicate the current status of the
processor pipeline and, as a result, are not related to the current bus transfer.
The PST value is updated each processor cycle.
MCF5235 Reference Manual, Rev. 2
Figure
Section 32.9, “Recommended BDM
32-2. PSTCLK indicates when the development system should
Description
Table 32-2
Pinout.”
External Signal Description
shows the
32-3