MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 479

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

data bytes, even if the DLC (data length code) value is bigger. Refer to
Message Buffers
21.4.3 Receive Process
The CPU prepares or changes an MB for frame reception by executing the following steps:
The first write to the control/status word is important in case there was a pending reception or
transmission. The write operation immediately deactivates the MB, removing it from any currently
ongoing arbitration or matching process, giving time for the CPU to program the rest of the MB.
Once the MB is activated in the third step, it will be able to receive CAN frames that match the
programmed ID. At the end of a successful reception, the
written into the Time Stamp field, the received ID, data (8 bytes at most) and length fields are
stored, the CODE field in the control and status word is updated (see
flag is set in the IFLAGn register and an interrupt is generated if allowed by the corresponding
IMASKn bit.
The CPU should read a receive frame from its MB in the following way:
Upon reading the control and status word, if the BUSY bit is set in the CODE field, then the CPU
should defer the access to the MB until this bit is negated. Reading the free running timer is not
mandatory. If not executed the MB remains locked, unless the CPU reads the C/S word of another
MB. Note that only a single MB is locked at a time. The only mandatory CPU read operation is
the one on the control and status word to assure data coherency.
The CPU should synchronize to frame reception by an IFLAGn bit for the specific MB (see
Section 21.3.2.8, “Interrupt Flag Register
field for that MB. Polling the CODE field does not work because once a frame was received and
the CPU services the MB (by reading the C/S word followed by unlocking the MB), the CODE
field will not return to EMPTY. It will remain FULL, as explained in
to workaround this behavior by writing to the C/S word to force an EMPTY code after reading the
MB, the MB is actually deactivated from any currently ongoing matching process. As a result, a
Freescale Semiconductor
1. Writing the control/status word to hold Rx MB inactive (CODE = 0000).
2. Writing the ID word.
3. Writing the control/status word to mark the Rx MB as active and empty (CODE = 1000).
1. Read the control/status word (mandatory—activates internal lock for this buffer).
2. Read the ID (Optional—needed only if a mask was used).
3. Read the Data field words.
4. Read the free-running timer (Releases internal lock —optional).
The first and last steps are mandatory!
(SMBs)” for more information on serial message buffers.
MCF5235 Reference Manual, Rev. 2
(IFLAGn)”), and not by the control/status word CODE
NOTE
value of the free running timer (TIMERn) is
Table
Table
Section 21.4.5.1, “Serial
21-13. If the CPU tries
21-13), and a status
Functional Overview
21-25