MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 472
MOD5234-100IR
Manufacturer Part Number
MOD5234-100IR
Description
MOD5234 10/100 ETHERNET MODULE
Manufacturer
NetBurner Inc
Type
Controllers & Processorsr
Datasheets
1.MOD5272-100IR.pdf
(3 pages)
2.MOD5234-100IR.pdf
(4 pages)
3.MOD5234-100IR.pdf
(754 pages)
Specifications of MOD5234-100IR
Interface
I²C, SPI, UART
Voltage - Supply
2.5V
Mounting Type
Surface Mount
Package / Case
Module
Product
Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Format
-
Baud Rates
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q4483564
- Current page: 472 of 754
- Download datasheet (13Mb)
FlexCAN
21.3.2.7 Interrupt Mask Register (IMASKn)
IMASKn contains one interrupt mask bit per buffer. It enables the CPU to determine which buffer
will generate an interrupt after a successful transmission/reception (that is, when the
corresponding IFLAGn bit is set).
21.3.2.8 Interrupt Flag Register (IFLAGn)
IFLAGn contains one interrupt flag bit per buffer. Each successful transmission/reception sets the
corresponding IFLAGn bit and, if the corresponding IMASKn bit is set, will generate an interrupt.
21-18
Reg Addr
Reset
Reset
31–16
15–0
Bits
Bits
1
0
W
W
R
R
31
15
0
0
0
ERRINT
BUFnM
Name
Name
—
30
14
—
0
0
0
Table 21-8. FlexCAN Interrupt Mask Register (IMASKn)
Table 21-7. ERRSTATn Field Descriptions (Continued)
29
13
0
0
0
Error interrupt. Indicates that at least one of the ERRSTATn[15:10] bits is set. The user
must write a 1 to clear this bit. Writing 0 has no effect.
0 No error interrupt request.
1 At least one of the error bits is set. If the CANCTRLn[ERRMSK] bit is set, an interrupt
Reserved, should be cleared.
Reserved, should be cleared.
Buffer interrupt mask. Enables the respective FlexCAN message buffer (MB0 to MB15)
interrupt. These bits allow the CPU to designate which buffers will generate interrupts after
successful transmission/reception.
0 The interrupt for the corresponding buffer is disabled.
1 The interrupt for the corresponding buffer is enabled.
Note: Setting or clearing an IMASKn bit can assert or negate an interrupt request, if the
corresponding IFLAGn bit it is set.
request is generated.
Table 21-9. IMASKn Field Descriptions
28
12
0
0
0
IPSBAR + 0x1C_002A (CAN0); 0x1F_002A (CAN1)
MCF5235 Reference Manual, Rev. 2
27
11
0
0
0
26
10
0
0
0
25
0
0
0
9
BUFnM
24
0
0
0
8
Description
Description
23
0
0
0
7
22
0
0
0
6
21
0
0
0
5
20
0
0
0
4
19
0
0
0
3
Freescale Semiconductor
18
0
0
0
2
17
0
0
0
1
16
0
0
0
0
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