MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 641

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

31.4.3.1 EXTEST Instruction
The external test (EXTEST) instruction selects the boundary scan register. It forces all output pins
and bidirectional pins configured as outputs to the values preloaded with the
SAMPLE/PRELOAD instruction and held in the boundary scan update registers. EXTEST can
also configure the direction of bidirectional pins and establish high-impedance states on some
pins. EXTEST asserts internal reset for the MCU system logic to force a predictable internal state
while performing external boundary scan operations.
31.4.3.2 IDCODE Instruction
The IDCODE instruction selects the 32-bit IDCODE register for connection as a shift path
between the TDI and TDO pin. This instruction allows interrogation of the MCU to determine its
version number and other part identification data. The shift register lsb is forced to logic 1 on the
rising edge of TCLK following entry into the capture-DR state. Therefore, the first bit to be shifted
out after selecting the IDCODE register is always a logic 1. The remaining 31 bits are also forced
to fixed values on the rising edge of TCLK following entry into the capture-DR state.
IDCODE is the default instruction placed into the instruction register when the TAP resets. Thus,
after a TAP reset, the IDCODE register is selected automatically.
31.4.3.3 SAMPLE Instruction
The SAMPLE instruction obtains a sample of the system data and control signals present at the
MCU input pins and just before the boundary scan cell at the output pins. This sampling occurs on
the rising edge of TCLK in the capture-DR state when the IR contains the $2 opcode. The sampled
Freescale Semiconductor
ACCESS_AUX_TAP_eTPU
1
Freescale reserves the right to change the decoding of the unused opcodes in the future.
ENABLE_TEST_CTRL
Instruction
Reserved
SAMPLE
BYPASS
EXTEST
CLAMP
HIGHZ
Table 31-5. JTAG Instructions (Continued)
all others
IR[4:0]
00011
00100
00110
01001
01100
10000
11111
MCF5235 Reference Manual, Rev. 2
Selects boundary scan register for shifting and sampling without disturbing
functional operation
Selects boundary scan register while applying fixed values to output pins and
asserting functional reset
Selects TEST_CTRL register
Selects bypass register while tri-stating all output pins and asserting
functional reset
Selects bypass while applying fixed values to output pins and asserting
functional reset
Enables access to the eTPU Nexus TAP controller
Selects bypass register for data operations
Decoded to select bypass register
Instruction Summary
1
Functional Description
31-9