MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 669

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

The sequence is as follows:
Freescale Semiconductor
• In cycle 1, the development system command is issued (
• In cycle 2, the development system supplies the high-order 16 address bits. The debug
• In cycle 3, the development system supplies the low-order 16 address bits. The debug
• At the completion of cycle 3, the debug module initiates a memory read operation. Any
• Results are returned in the two serial transfer cycles after the memory access completes. For
READ (LONG)
Commands transmitted to the debug module
Responses from the debug module
module responds with either the low-order results of the previous command or a command
complete status of the previous command, if no results are required.
module returns a not-ready response unless the received command is decoded as
unimplemented, which is indicated by the illegal command encoding. If this occurs, the
development system should retransmit the command.
module always returns a not-ready response.
serial transfers that begin during a memory access return a not-ready response.
any command performing a byte-sized memory read operation, the upper 8 bits of the
response data are undefined and the referenced data is returned in the lower 8 bits. The next
command’s opcode is sent to the debug module during the final transfer. If a memory or
???
Command code transmitted during this cycle
A
memory-referencing cycle. Otherwise, the debug module can accept a
new serial transfer after 32 processor clock periods.
Results from previous command
not-ready
’NOT READY’
MS ADDR
’ILLEGAL’
Sequence taken if illegal command
is received by debug module
Figure 32-16. Command Sequence Diagram
XXX
High-order 16 bits of memory address
response
MCF5235 Reference Manual, Rev. 2
’NOT READY’
’NOT READY’
Data used from this transfer
NEXT CMD
LS ADDR
can
Low-order 16 bits of memory address
NOTE
be
Non-serial-related
LOCATION
ignored
MEMORY
activity
READ
READ
except
’NOT READY’
MS RESULT
Sequence taken if bus error
occurs on memory access
ColdFire Background Debug Mode (BDM)
Sequence taken if operation
has not completed
High- and low-order 16 bits of result
in this example). The debug
BERR
XXX
XXX
XXX
during
’NOT READY’
a
LS RESULT
NEXT CMD
NEXT CMD
Command
Code
Next
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