MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 439

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

20.6.2.2.2 eTPU Time Base 1 (TCR1) Visibility Register (ETPU_TB1R)
This register provides visibility of the TCR1 time base for CPU host read access. This register is
read-only. The value of the TCR1 time base shown can be driven by the TCR1 counter or
imported, depending on the configuration set in ETPU_REDCR. For more information, refer to
the eTPU User’s Manual.
Freescale Semiconductor
24–22
21–16
15-8
Bits
7–0
25
TCR1CTL
Table 20-7. ETPU_TBCR Field Descriptions (Continued)
TCR2P
TCR1P
Name
AM
—
provides angle information to the channels using the TCR2 bus. When the AM is
cleared (non-angle mode), EAC operation is disabled, and its internal registers can be
used as general purpose registers.
0 EAC operation is disabled.
1 TCR2 works in angle mode. The EAC works and stores tooth counter and angle tick
For more information, refer to the eTPU User’s Manual.
Reserved.
Timer count register 2 prescaler control. Part of the TCR2 clocking system. TCR2 is
clocked from the output of a prescaler. The prescaler divides its input by (TCR2P+1)
allowing frequency divisions from 1 to 64. The prescaler input is the internal bus clock
divided by 8 (in gated or non-gated clock mode) or TCRCLK filtered input. For more
information on TCR2, refer to the eTPU User’s Manual.
TCR1 clock/gate control. Part of the TCR1 clocking system. It determines the clock
source for TCR1. TCR1 can count on detected rising edge of the TCRFCLK signal or
the internal bus clock divided by 2. After reset TCRCLK signal is selected. The
following table shows the selection of the TCR1 clock source.
For more information on the TCR1 clocking system, refer to the eTPU User’s Manual.
Timer count register 1 prescaler control. Clocked from the output of a prescaler. The
input to the prescaler is the internal eTPU system clock divided by 2 or the output of
TCRCLK filter. The prescaler divides this input by (TCR1P+1) allowing frequency
divisions from 1 up to 256.
Angle mode selection. When the AM bit is set the EAC (eTPU Angle Clock) hardware
counter data in TCR2.
TCR1CTL
00
01
10
11
MCF5235 Reference Manual, Rev. 2
selects TCRCLK as clock source for the TCR1 prescaler
reserved
selects internal bus clock divided by 2 as clock source for
the TCR1 prescaler
reserved
Description
TCR1 Clock
Memory Map/Register Definition
20-25