MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 600
![MOD5234 10/100 ETHERNET MODULE](/photos/28/91/289101/mod-100ir_sml.jpg)
MOD5234-100IR
Manufacturer Part Number
MOD5234-100IR
Description
MOD5234 10/100 ETHERNET MODULE
Manufacturer
NetBurner Inc
Type
Controllers & Processorsr
Datasheets
1.MOD5272-100IR.pdf
(3 pages)
2.MOD5234-100IR.pdf
(4 pages)
3.MOD5234-100IR.pdf
(754 pages)
Specifications of MOD5234-100IR
Interface
I²C, SPI, UART
Voltage - Supply
2.5V
Mounting Type
Surface Mount
Package / Case
Module
Product
Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Format
-
Baud Rates
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q4483564
- Current page: 600 of 754
- Download datasheet (13Mb)
Message Digest Hardware Accelerator (MDHA)
28.3.1
The MDHA Top Control block enables the FIFO whenever the MDHA module is enabled. This
block also captures both error and done status from the MDHA Logic block and generates a single
interrupt to the interrupt controller.
28.3.2
The FIFO block contains a 16 × 32-bit FIFO that is used for temporary storage of the data to be
hashed.
28.3.3
The MDHA logic block consists of 7 sub-blocks: the address decoder, interface control,
auto-padder, auto-padder control, algorithm engine, algorithm engine control, and status interrupt
as shown in
28.3.3.1 Address Decoder
The address decoder drives out the proper data from the module or captures incoming data into the
appropriate register.
28.3.3.2 Interface Control
The interface block decodes the MDMR and outputs all control signals to all other blocks. Control
signals are received from other modules to send a pop signal to the FIFO.
28.3.3.3 Auto-Padder
The Auto-padder takes longwords in from the FIFO and then either passes it directly to the engine
or pads the word according to the control bits that are set. The IPAD and OPAD is done to all
longwords in this block before they are passed directly to the engine. This block takes care of
passing the proper data to the engine for the EHMAC mode of operation. This is done by an
internal counter that will leave 351 bits in the Input FIFO.
28.3.3.4 Hashing Engine
This module is the core of the Message Digest Hardware Accelerator that is capable of computing
the Secure Hash Algorithm (SHA-1) or Message Digest 5 (MD5).
28-14
MDHA Top Control
FIFO
MDHA Logic
Figure
28-11.
MCF5235 Reference Manual, Rev. 2
Freescale Semiconductor
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