MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 357

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Memory Map/Register Definition
18.3.5.1 Mode Register Settings
It is possible to configure the operation of SDRAMs, namely their burst operation and SD_SCAS
latency, through the SDRAM component’s mode register. SD_SCAS latency is a function of the
speed of the SDRAM and the bus clock of the DRAM controller. The DRAM controller operates
at a SD_SCAS latency of 1, 2, or 3.
Although the MCF5235 DRAM controller supports bursting operations, it does not use the
bursting features of the SDRAMs. Because the MCF5235 can burst operand sizes of 1, 2, 4, or 16
bytes long, the concept of a fixed burst length in the SDRAMs mode register becomes problematic.
Therefore, the MCF5235 DRAM controller generates the burst cycles rather than the SDRAM
device. Because the MCF5235 generates a new address and a
or
command for each
READ
WRITE
transfer within the burst, the SDRAM mode register should be set either not to burst or to a burst
length of one. This allows bursting to be controlled by the MCF5235.
The SDRAM mode register is written by setting the associated block’s DACR[IMRS]. First, the
base address and mask registers must be set to the appropriate configuration to allow the mode
register to be set. Note that improperly set DMR mask bits may prevent access to the mode register
address. Thus, the user should determine the mapping of the mode register address to the
MCF5235 address bits to find out if an access is blocked. If the DMR setting prohibits mode
register access, the DMR should be reconfigured to enable the access and then set to its necessary
configuration after the
command executes.
MRS
The associated CBM bits should also be initialized. After DACR[IMRS] is set, the next access to
the SDRAM address space generates the
command to that SDRAM. The address of the access
MRS
should be selected to place the correct mode information on the SDRAM address pins. The address
is not multiplexed for the
command. The
access can be a read or write. The important
MRS
MRS
thing is that the address output of that access needs the correct mode programming information on
the correct address bits.
Figure 18-10
shows the
command, which occurs in the first clock of the bus cycle.
MRS
MCF5235 Reference Manual, Rev. 2
Freescale Semiconductor
18-19