MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 213

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

11.2.1 Register Descriptions
11.2.1.1 Internal Peripheral System Base Address Register (IPSBAR)
The IPSBAR specifies the base address for the 1 Gbyte memory space associated with the on-chip
peripherals. At reset, the base address is loaded with a default location of 0x4000_0000 and
marked as valid (IPSBAR[V]=1). If desired, the address space associated with the internal
modules can be moved by loading a different value into the IPSBAR at a later time.
If an address “hits” in overlapping memory regions, the following priority is used to determine
what memory is accessed:
See
Freescale Semiconductor
1. IPSBAR
2. RAMBAR
3. Cache
4. SDRAM
5. Chip Selects
Figure 11-1
This is the list of memory access priorities when viewed from the
processor core.
1
2
0x00_003C
0x00_0030
0x00_0034
0x00_0038
and
IPSBAR
The LPICR register is described in
The DMAREQC register is described in
Offset
Table 11-2
Table 11-1. SCM Register Map (Continued)
GPACR
[31:24]
—
—
—
for descriptions of the bits in IPSBAR.
MCF5235 Reference Manual, Rev. 2
[23:16]
Chapter 8, “Power
NOTE
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Chapter 14, “DMA Controller
[15:8]
Management."
—
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Module.”
[7:0]
Memory Map/Register Definition
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11-3