MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 611
MOD5234-100IR
Manufacturer Part Number
MOD5234-100IR
Description
MOD5234 10/100 ETHERNET MODULE
Manufacturer
NetBurner Inc
Type
Controllers & Processorsr
Datasheets
1.MOD5272-100IR.pdf
(3 pages)
2.MOD5234-100IR.pdf
(4 pages)
3.MOD5234-100IR.pdf
(754 pages)
Specifications of MOD5234-100IR
Interface
I²C, SPI, UART
Voltage - Supply
2.5V
Mounting Type
Surface Mount
Package / Case
Module
Product
Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Format
-
Baud Rates
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q4483564
- Current page: 611 of 754
- Download datasheet (13Mb)
29.3
The RNG has three functional blocks. They are the Output FIFO, internal bus interface and the
RNG Core/Control Logic blocks, as shown in
blocks in more detail.
29.3.1 Output FIFO
The Output FIFO provides temporary storage for random data generated by the RNG Core/Control
Logic block. This allows the user to read multiple random long words back to back. The RNGSR,
allows the user to monitor the number of random words in the FIFO through the Output FIFO
Level field. If the user reads from the FIFO when it is empty and the interrupt is enabled, the RNG
will drive an interrupt request to the interrupt controller. It is very important that the user polls the
RNGSR[OFL] bit to make sure random values are present before reading from the FIFO.
29.3.2 RNG Core/Control Logic Block
This block contains the RNG’s control logic as well as its core engine used to generate random
data.
29.3.3 RNG Control Block
The Control Block contains the address decoder, all addressable registers, and control state
machines for the RNG. This block is responsible for communication with both the peripheral
interface and the FIFO interface. The block also controls the Core Engine to generate random data.
The general functionality of the block is as follows. After reset, entropy is generated and stored in
the RNG’s shift registers. After the GO Bit is set in the RNGCR, the FIFO is loaded with a random
word every 256 cycles. The process of loading the FIFO continues as long as the FIFO is not full.
Freescale Semiconductor
Functional Description
Output FIFO
RNG Core/Control
Logic
Figure 29-5. RNG Block Diagram
MCF5235 Reference Manual, Rev. 2
Figure
Random Number
Generator
29-5. The following sections describe these
Internal Bus
Internal
Control
Signals
Functional Description
29-5
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