MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 49

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

1.3.2
The processor core is comprised of two separate pipelines that are decoupled by an instruction
buffer. The two-stage Instruction Fetch Pipeline (IFP) is responsible for instruction-address
generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that
holds prefetched instructions awaiting execution in the Operand Execution Pipeline (OEP). The
OEP includes two pipeline stages. The first stage decodes instructions and selects operands
(DSOC); the second stage (AGEX) performs instruction execution and calculates operand
effective addresses, if needed.
The V2 core implements the ColdFire Instruction Set Architecture Revision A with added support
for a separate user stack pointer register and four new instructions to assist in bit processing.
Additionally, the MCF5235 core includes the enhanced multiply-accumulate unit (EMAC) for
improved signal processing capabilities. The EMAC implements a 4-stage execution pipeline,
optimized for 32 x 32 bit operations, with support for four 48-bit accumulators. Supported
operands include 16- and 32-bit signed and unsigned integers as well as signed fractional operands
and a complete set of instructions to process these data types. The EMAC provides superb support
for execution of DSP operations within the context of a single processor at a minimal hardware
cost.
1.3.3
The eTPU is an intelligent programmable I/O controller with its own core and memory system,
allowing it to perform complex timing and I/O management independently of the CPU. The eTPU
is essentially a co-processor designed for timing control, I/O handling, serial communications,
motor control. and engine control applications and accesses data without the host CPU’s
Freescale Semiconductor
• General Purpose I/O interface
• JTAG support for system level board testing
— Sets boot device and its data port width
— Configures output pad drive strength
— Unique part identification number and part revision number
— Reset
— Up to 142 bits of general purpose I/O
— Bit manipulation supported via set/clear functions
— Unused peripheral pins may be used as extra GPIO
– Separate reset in and reset out signals
– Six sources of reset: Power-on reset (POR), External, Software, Watchdog, PLL loss
– Status flag indication of source of last reset
V2 Core Overview
Enhanced Time Processor Unit (eTPU)
of clock, PLL loss of lock
MCF5235 Reference Manual, Rev. 2
Features
1-9