MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 744

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

External interface module (EIM), see bus
F
Fault-on-fault 3-16
FEC, see Ethernet
FlexCAN
Free Running Timer 21-24
G
GPIO
Index-4
overview 3-9
privilege violation 3-14
reset 3-16
trace 3-14
TRAP instruction 3-15
bit timing 21-30
initialization 21-32
interrupts 21-33
memory map 21-6
message buffers
operation 21-23
receive process 21-25
registers
signals 21-6
transmit process 21-23
block diagram 12-2
frames
handling 21-27
receive
serial 21-24
time stamp 21-30
transmit
freeze mode 21-4
listen-only mode 21-5
loop-back mode 21-5
low-power modes 8-10
module disabled mode 21-5
normal mode 21-4
control (CANCTRLn) 21-9
error and status (ERRSTATn) 21-16
error counter (ERRCNTn) 21-14
interrupt flag (IFLAGn) 21-18
interrupt mask (IMASKn) 21-18
overload 21-29
remote 21-29
self-received 21-26
locking and releasing 21-28
serial message buffers 21-27
transmit deactivation 21-27
codes 21-22
codes 21-22
priority 21-24
–
21-32
,
21-25
MCF5235 Reference Manual, Rev. 2
I
I
Instructions
2
C
memory map 12-10
operation
registers
arbitration procedure 27-6
clock
handshaking 27-8
memory map 27-8
operation 27-3
programming examples
registers
slave mode 27-16
additions 3-9
enhancements
execution timing
JTAG
low-power modes 8-9
drive strength control (DSCR_x) 12-30
pin assignment (PARx) 12-20
port clear output data (PCLRR_x) 12-18
port data direction (PDDR_x) 12-14
port output data (PODR_x) 12-12
port pin data/set data (PPDSDR_x) 12-16
arbitration 27-6
stretching 27-8
synchronization 27-6
low-power modes 8-7
initialization 27-13
repeated START generation 27-16
START generation 27-14
STOP generation 27-15
address (I2ADR) 27-8
control (I2CR) 27-10
data I/O (I2DR) 27-12
frequency divider (I2FDR) 27-9
status (I2SR) 27-11
BITREV 3-27
BYTEREV 3-28
FF1 3-29
STRLDSR 3-30
branch 3-26
EMAC 3-25
miscellaneous 3-24
MOVE 3-20
one-operand 3-21
two-operand 3-22
ACCESS_AUX_TAP 31-11
BYPASS 31-10
CLAMP 31-10
Freescale Semiconductor