MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 262
MOD5234-100IR
Manufacturer Part Number
MOD5234-100IR
Description
MOD5234 10/100 ETHERNET MODULE
Manufacturer
NetBurner Inc
Type
Controllers & Processorsr
Datasheets
1.MOD5272-100IR.pdf
(3 pages)
2.MOD5234-100IR.pdf
(4 pages)
3.MOD5234-100IR.pdf
(754 pages)
Specifications of MOD5234-100IR
Interface
I²C, SPI, UART
Voltage - Supply
2.5V
Mounting Type
Surface Mount
Package / Case
Module
Product
Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Format
-
Baud Rates
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q4483564
- Current page: 262 of 754
- Download datasheet (13Mb)
General Purpose I/O Module
12.3.1.8.6 Timer Drive Strength Control Register (DSCR_TIMER)
The DSCR_TIMER register controls the output drive strengths of the following pins: DT3IN,
DT3OUT, DT2IN, DT2OUT, DT1IN, DT1OUT, DT0IN, and DT0OUT.
12.4
12.4.1 Overview
Initial pin function is determined during reset configuration. The pin assignment registers allow
the user to select among various primary functions and general purpose I/O after reset.
Most pins are configured as general purpose I/O by default. The notable exceptions to this are
external bus control pins, address/data pins, and chip select pins. These pins are configured for
their primary functions after reset.
Every general purpose I/O pin is individually configurable as an input or an output via a data
direction register (PDDR_x).
Every GPIO port has an output data register (PODR_x) and a pin data register (PPDSDR_x) to
monitor and control the state of its pins. Data written to a PODR_x register is stored and then
driven to the corresponding port x pins configured as outputs.
Reading a PODR_x register returns the current state of the register regardless of the state of the
corresponding pins.
12-34
Bits
7–1
0
Functional Description
Figure 12-49. Timer Drive Strength Control Register (DSCR_TIMER)
DSCR_
TIMER
Name
Address
—
Reset
W
R
Table 12-24. DSCR_TIMER Field Descriptions
Note: Reset state is 0 when RCON = 1 and is the value of D[21] when
RCON = 0
Reserved, should be cleared.
Timer drive strength. This bit sets the drive strength on the DT3IN, DT3OUT, DT2IN,
DT2OUT, DT1IN, DT1OUT, DT0IN, and DT0OUT pins.
0 Pins set at low drive
1 Pins set at high drive
0
0
7
0
0
6
MCF5235 Reference Manual, Rev. 2
0
0
5
IPSBAR + 0x10_0055
0
0
4
Description
0
0
3
2
0
0
1
0
0
See Note
DSCR_
TIMER
0
Freescale Semiconductor
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