MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 545
MOD5234-100IR
Manufacturer Part Number
MOD5234-100IR
Description
MOD5234 10/100 ETHERNET MODULE
Manufacturer
NetBurner Inc
Type
Controllers & Processorsr
Datasheets
1.MOD5272-100IR.pdf
(3 pages)
2.MOD5234-100IR.pdf
(4 pages)
3.MOD5234-100IR.pdf
(754 pages)
Specifications of MOD5234-100IR
Interface
I²C, SPI, UART
Voltage - Supply
2.5V
Mounting Type
Surface Mount
Package / Case
Module
Product
Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Format
-
Baud Rates
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q4483564
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26.3.8
The UIPCRs, shown in
26.3.9
The UACRs, shown in
Freescale Semiconductor
Bits
7–5
3–1
4
0
UART Input Port Change Registers (UIPCRn)
UART Auxiliary Control Register (UACRn)
Name
Figure 26-10. UART Input Port Change Register (UIPCRn)
COS
CTS
Address
Address IPSBAR + 0x0210 (UIPCR0); IPSBAR + 0x0250 (UIPCR1); IPSBAR +
—
—
Reset
Reset
W
W
R
R
Figure
Figure
Reserved, should be cleared.
Change of state (high-to-low or low-to-high transition).
0 No change-of-state since the CPU last read UIPCRn. Reading UIPCRn clears
1 A change-of-state longer than 25–50 µs occurred on the UnCTS input. UACRn can be
Reserved, should be cleared.
Current state of clear-to-send. Starting two serial clock periods after reset, CTS reflects the
state of UnCTS. If UnCTS is detected asserted at that time, COS is set, which initiates an
interrupt if UACRn[IEC] is enabled.
0 The current state of the UnCTS input is asserted.
1 The current state of the UnCTS input is deasserted.
Figure 26-9. UART Transmit Buffer (UTBn)
UISRn[COS].
programmed to generate an interrupt to the CPU when a change of state is detected.
0
0
0
7
7
Table 26-8. UIPCRn Field Descriptions
26-8, control the input enable.
26-10, hold the current state and the change-of-state for UnCTS.
IPSBAR + 0x020C(UTB0); IPSBAR + 0x024C(UTB1);
MCF5235 Reference Manual, Rev. 2
0
0
0
6
6
0
0
0
5
5
IPSBAR + 0x028C(UTB2)
0x0290 (UIPCR2)
COS
0
0
4
4
TB
Description
0
0
1
3
3
2
0
2
0
1
0
0
1
1
1
Memory Map/Register Definition
UnCTS
CTS
0
0
0
26-13
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