MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 354

MOD5234 10/100 ETHERNET MODULE

MOD5234-100IR

Manufacturer Part Number
MOD5234-100IR
Description
MOD5234 10/100 ETHERNET MODULE
Manufacturer
NetBurner Inc
Type
Controllers & Processorsr

Specifications of MOD5234-100IR

Interface
I²C, SPI, UART
Voltage - Supply
2.5V
Mounting Type
Surface Mount
Package / Case
Module
Product
Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Format
-
Baud Rates
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q4483564
Synchronous DRAM Controller Module
Accesses in synchronous burst page mode always cause the following sequence:
18.3.4.4 Auto-Refresh Operation
The DRAM controller is equipped with a refresh counter and control. This logic is responsible for
providing timing and control to refresh the SDRAM without user interaction. Once the refresh
counter is set, and refresh is enabled, the counter counts to zero. At this time, an internal refresh
18-16
SDRAM_CS[0] or [1]
1.
2.
3. Required number of
4. Some transfers need more
5.
6. Required number of idle clocks inserted to assure precharge-to-
ACTV
NOP
NOP
port size.
PALL
DQM[3:0]
SYSCLK
DRAMW
commands to assure SD_SRAS-to-SD_SCAS delay (if CAS latency is 1, there are no
commands).
D[31:0]
A[31:0]
command
command
SRAS
SCAS
OE
t
CASL
ACTV
Row
Figure 18-7. Burst Write SDRAM Access
= 2
READ
NOP
NOP
or
MCF5235 Reference Manual, Rev. 2
Column
WRITE
WRITE
commands to assure the
commands to service the transfer size with the given
Column Column
WRITE
WRITE
t
RWL
WRITE
ACTV
Column
-to-precharge delay.
NOP
ACTV
PALL
delay.
Freescale Semiconductor
t
RP

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