MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 509

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

24.2.9 DMA Timer Reference Registers (DTRRn)
Each DTRRn, shown in
free-running timer counter (DTCNn) as part of the output-compare function. The reference value
is not matched until DTCNn equals DTRRn, and the prescaler indicates that DTCNn should be
incremented again. Thus, the reference register is matched after DTRRn+1 time intervals.
Freescale Semiconductor
Bits
7–2
1
0
Name
REF
CAP
—
Reserved, should be cleared.
Output reference event. The counter value, DTCNn, equals the reference value, DTRRn.
Writing a one to REF clears the event condition. Writing a zero has no effect.
Capture event. The counter value has been latched into DTCRn. Writing a one to CAP
clears the event condition. Writing a zero has no effect.
Figure
Table 24-4. DTERn Field Descriptions
CAP
0
1
1
1
1
1
1
1
1
24-5, contains the reference value compared with the respective
REF
0
1
1
1
1
MCF5235 Reference Manual, Rev. 2
DTMRn[CE]
00
00
01
01
10
10
11
11
DTMRn[ORRI]
X
X
0
0
1
1
[DMAEN]
DTXMRn
X
0
1
0
1
0
1
0
1
DTXMRn[DMAEN]
Description
Capture on falling edge & trigger interrupt
Capture on rising edge & trigger interrupt
Capture on any edge & trigger interrupt
Capture on falling edge & trigger DMA
Capture on rising edge & trigger DMA
X
Capture on any edge & trigger DMA
0
1
0
1
Disable capture event output
Disable capture event output
Interrupt request asserted
No event
DMA request asserted
No request asserted
No request asserted
Memory Map/Register Definition
No event
24-7