TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 763

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

Symbol
I2S0CTL
I2S1CTL
I2S0C
I2S1C
(22) I
2
I
Control
Register0
I
Divider
Value
Setting
Register
I
Control
Register1
I
Divider
Value
Setting
Register
2
2
2
2
S (2/2)
S
S0
S
S1
Name
Address
1808H
1809H
180AH
180BH
1818H
1819H
181AH
181BH
Transmit
0: Stop
1: Start
Source
clock
0: f
1: f
Transmit
0: Stop
1: Start
Source
clock
0: f
1: f
CLKS0
CLKS1
TXE0
CK07
TXE1
CK17
R/W
SYS
PLL
SYS
PLL
R/W
R/W
R/W
7
0
0
0
0
0
0
Counter
control
0: Clear
1: Start
Counter
control
0: Clear
1: Start
*CNTE0
*CNTE1
CK06
CK16
R/W
R/W
6
0
0
0
0
92CF26A-762
Set divide frequency for CK signal (8-bit counter)
WS05
WS15
CK05
CK15
Divider value for CK signal (8-bit counter)
5
0
0
0
0
Set divided frequency for WS signal (6-bit counter)
Transmissi
-on start
BIT
0:MSB
1:LSB
Stereo
/monaural
0: Stereo
1:Monaural
Transmissio-
n start BIT
0:MSB
1:LSB
Stereo
/monaural
0: Stereo
1:Monaural
FSEL0
FSEL1
WS04
WS14
CK04
Divider value for WS signal (6-bit counter)
CK14
DIR0
DIR1
R/W
R/W
R/W
R/W
4
0
0
0
0
0
0
0
0
R/W
R/W
Bit length
0: 8 bits
1:16 bits
Condition of
transmission
FIFO
0: data
1: None
data
Bit length
0: 8 bits
1:16 bits
Condition of
transmission
FIFO
0: data
1: None
data
TEMP0
TEMP1
WS03
WS13
CK03
CK13
BIT0
BIT1
R/W
R/W
3
R
R
0
1
0
0
0
1
0
0
R/W
R/W
Output format
00: I
10: Right
01: Left
11:Reserved
WS level
0:low left
1:high left
Output format
00: I
10: Right
01: Left
11:Reserved
WS level
0:low left
1:high left
DTFMT01 DTFMT00 SYSCKE0
DTFMT11 DTFMT10 SYSCKE1
WLVL0
WLVL1
WS02
WS12
CK02
CK12
R/W
R/W
R/W
R/W
2
2
2
0
0
0
0
0
0
0
0
S
S
Clock edge
for data
output
0:Rising
1:Falling
Clock edge
for data
output
0:Rising
1:Falling
EDGE0
EDGE1
WS01
WS11
CK01
CK11
R/W
R/W
R/W
R/W
TMP92CF26A
1
0
0
0
0
0
0
0
0
2007-11-21
System
clock
0:Disable
1:Enable
Clock enable
(After trans-
mission)
0:Operate
1:Stop
System
clock
0:Disable
1:Enable
Clock enable
(After trans-
mission)
0:Operate
1:Stop
CLKE0
CLKE1
WS00
WS10
CK00
CK10
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0