TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 511

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

I2S0C
(180AH)
(180BH)
bit Symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
Note: The transfer clock must not exceed 10 MHz. Make sure that the transfer clock is set to within 10 MHz by an
Note: It is recommended that the value to be set in I2SnC<CKn7:0> be an even number. Although it is possible to set
(3) Setting example for the clock generator (8-bit counter/6-bit counter)
appropriate combination of source clock frequency and divider value.
an odd number, the clock duty of the CK signal does not become 50%. Setting an odd number causes the High
width of the I2SnCK0 signal to become longer by one f
0, the Low width becomes longer than the High width.)
When f
follows:
and sampling frequency.
The clock generator generates the reference clock for setting the data transfer speed
•
CK07
<CLKSn>. An 8-bit counter is provided to divide the source clock by 3 to 256. (The
divider value cannot be set to 1 or 2.)
15
8-bit counter set value
I2SnCKO = f
7
0
The transfer clock is generated by dividing the clock selected by I2SnCTL
SYS
Setting the transfer clock I2SnCKO
00000000
00000001
11111111
= 60 MHz and I2SnC<CKn7:0> = 150, the data transfer speed is set as
CK06
14
6
0
= 60 [MHz]/150 = 400 [kbps]
SYS
/150
WS05
CK05
Divider value for CK signal (8-bit counter)
13
5
0
0
92CF26A-510
WS04
CK04
Divider value for WS signal (6-bit counter)
12
4
0
0
R/W
SYS
WS03
CK03
or f
11
3
0
0
Divider value
PLL
256
1
255
R/W
pulse than the Low width. (When <EDGE> =
WS02
CK02
10
2
0
0
WS01
CK01
1
9
0
0
TMP92CF26A
WS00
CK00
0
8
0
0
2007-11-21