TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 110

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

HDMATR
(097FH)
Bit Symbol
Read/Write
Reset State
Function
Note: Read-modify-write instructions can be used on this register.
Note: To be precise, the bus assert time and RAM access time are added each time the HDMA transfer time is
(256 × 6 × (1 / f
Sample 5: Calculation example when using CPU + LCDC + SDRAMC + HDMA at
Conditions:
Calculation example:
t
By writing “86H” to the HDMATR register, the maximum HDMA time is set to 19.2[μs]
STOP
forcefully terminated at 19.2 [μs].
time (maximum HDMA time) must be set to 19.8875 [μS] or less. Although transferring
all 225 Kbytes from the internal RAM to SDRAM requires t
the maximum HDMA time should be limited by using the HDMATR register.
Timer
operation
0: Disable
1:Enable
CPU operation speed (f
Display RAM
Display size
Display quality
Refresh rate
HDMA
LHSYNC [period: S] = 1/70 [Hz]/ (COM+20) = 54.9 [μS]
t
LCD driver data transfer time [S]
LHSYNC [cycle S] − LCD driver data transfer time [S] − t
To realize proper LCD display, the maximum time HDMA can occupy the bus at a
STOP
DMATE
(LCD)
7
0
same time (Worst case)
(HDMA) = (((2 + 1) × 4) × 57600) + 28800 + 14400)/ f
SYS
DMATR6
= ((SegNum × K/8) × t
)).
6
0
= ((320 × 24/8) × 1/f
= ((960) × 12.5 [nS]/4) + 12.5 [nS]
= 3.0125 [μS]
= SegNum × (1/ f
= 320 × (1/80MHz) × 8 = 32 [μS]
DMATR5
The value to be set in <DMATR6:0> should be obtained by
SYS
HDMATR register
5
0
92CF26A-109
: Internal RAM
: QVGA (320seg × 240com)
: 16777216 color (TFT)
: 70Hz
: Transfers 225 Kbytes from internal RAM to SDRAM
= 54.9 [μS] − 32 [μS] − 3.0125 [μS] = 19.8875 [μS]
“Maximum bus occupancy time / (256/f
)
Maximum bus occupancy time setting
DMATR4
4
SYS
0
LRD
: 80MHz
SYS
“00H” cannot be set.
) × (LD bus transfer speed)
R/W
) + (1/f
[Hz]/4) + (1/f
DMATR3
3
0
SYS
[Hz])
DMATR2
SYS
2
0
[Hz])
SYS
STOP
STOP
SYS
)”.
DMATR1
1
0
[S] = 9180 [μS]
(HDMA) = 9180 [μs],
(LCD)
TMP92CF26A
DMATR0
0
2007-11-21
0