TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 751

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

TA45MOD
TA67MOD
TA45RUN
TA5FFCR
TA67RUN
TA7FFCR
Symbol
TA4REG
TA5REG
TA6REG
TA7REG
(14) 8-bit timer (1/2)
TMRA45
RUN
register
8-bit timer
register 4
8-bit timer
register 5
TMRA45
MODE
register
TMRA5
Flip-Flop
control
register
TMRA67
RUN
register
8-bit timer
register 2
8-bit timer
register 3
TMRA67
MODE
register
TMRA7
Flip-Flop
control
register
Name
Address
(Prohibit
(Prohibit
(Prohibit
(Prohibit
(Prohibit
(Prohibit
111AH
111BH
111CH
111DH
1110H
1112H
1113H
1114H
1115H
1118H
RMW)
RMW)
RMW)
RMW)
RMW)
RMW)
Double
buffer
0: Disable
1: Enable
Operation mode
00: 8-bit timer mode
01: 16-bit timer mode
10: 8-bit PPG mode
11: 8-bit PWM mode
Double
buffer
0: Disable
1: Enable
Operation mode
00: 8-bit timer mode
01: 16-bit timer mode
10: 8-bit PPG mode
11: 8-bit PWM mode
TA6RDE
TA45M1
TA67M1
TA4RDE
R/W
R/W
0
0
0
7
0
TA45M0
TA67M0
0
0
6
92CF26A-750
PWM cycle
00: Reserved
01: 2
10: 2
11: 2
PWM cycle
00: Reserved
01: 2
10: 2
11: 2
PWM41
PWM61
5
0
6
7
8
0
6
7
8
PWM40
PWM60
4
0
0
R/W
R/W
W
W
W
W
−
0
−
0
−
0
−
0
IDLE2
0: Stop
1: Operate 0: Stop and clear
Source clock for TMRA5
00: TA4TRG
01: φ T1
10: φ T16
11: φ T256
00: Invert TA5FF
01: Set TA5FF
10: Clear TA5FF
11: Don’t care
IDLE2
0: Stop
1: Operate 0: Stop and clear
Source clock for TMRA7
00: TA6TRG
01: φ T1
10: φ T16
11: φ T256
00: Invert TA7FF
01: Set TA7FF
10: Clear TA7FF
11: Don’t care
TA5CLK1 TA5CLK0 TA4CLK1 TA4CLK0
TA5FFC1 TA5FFC0
TA7CLK1 TA7CLK0 TA6CLK1 TA6CLK0
TA7FFC1 TA7FFC0
I2TA45
I2TA67
3
0
0
1
0
0
1
W
W
TA45PRUN TA5RUN
TA67PRUN TA7RUN
TMRA45
prescaler
1: Run (Count up)
TMRA67
prescaler
1: Run (Count up)
2
0
0
1
0
0
1
R/W
R/W
Up counter
(UC5)
Source clock for TMRA4
00: 32KHz clock
01: φ T1
10: φ T4
11: φ T16
TA5FF
control for
inversion
0: Disable
1: Enable
Up counter
(UC7)
Source clock for TMRA6
00: 32KHz clock
01: φ T1
10: φ T4
11: φ T16
TA7FF
control for
inversion
0: Disable
1: Enable
TA5FFIE
TA7FFIE
TMP92CF26A
1
0
0
0
0
0
0
2007-11-21
R/W
R/W
Up counter
(UC4)
TA5FF
inversion
select
0: TMRA4
1: TMRA5
Up counter
(UC6)
TA7FF
inversion
select
0: TMRA6
1: TMRA7
TA4RUN
TA5FFIS
TA6RUN
TA7FFIS
0
0
0
0
0
0
0