TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 531

no-image

TMP92CF26AXBG

Manufacturer Part Number
TMP92CF26AXBG
Description
Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
Manufacturer
Toshiba
Datasheet

Specifications of TMP92CF26AXBG

Processor Series
TLCS-900
Core
900/H
Data Bus Width
16 bit
Program Memory Type
ROM
Program Memory Size
8 KB
Data Ram Size
144 KB
Interface Type
I2C, I2S, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
136
Number Of Timers
10
Maximum Operating Temperature
+ 50 C
Mounting Style
SMD/SMT
Package / Case
FBGA-228
Development Tools By Supplier
BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA
Quantity:
4 000
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
Internal signal (f
LD23-LD0
LD23-LD0
LD23-LD0
3.19.3.5 Reference Clock LCP0
LCP0
LCP0
LCP0
SYS
Minimum speed
Maximum speed
)
STN and setting LCDMODE0<SCPW1:0> and LCDMODE1<SWPW2>. The clock
speed should be selected to meet the characteristics of the LCD driver to be used.
and f
STN monochrome/grayscale
STN color
TFT
LCP0 is used as the reference clock for all the signals in the LCDC.
This section explains how to set the frequency (period) of the LCP0 signal.
The LCP0 clock speed (LD bus transfer speed) is determined by selecting TFT or
The LCP0 period can be selected from four types: f
overlapping the current line signal.
data cannot be transferred properly. Set the data transfer speed so that each
transfer completes within the LHSYNC period.
cannot be prepared in time, causing wrong data to be transferred. The maximum
transfer speed is limited by the operation mode and display RAM type (bus width,
wait condition, and so on). If the data rotation function is used, the transfer speed
must be slower.
SYS
The LCP0 period needs to be short enough to prevent the next line signal from
The transfer speed of display data must be set to suit the refresh rate; otherwise
If the LCP0 period is too short, the data to be transferred to the LCD driver
/48.
Figure 3.19.1 LCP Frequency Selection
:
:
:
92CF26A-530
Segment size / 8 × LCP0 [s: period] < LHSYNC [s: period] STN color
Segment size × 3 / 8 LCP0 [s: period] < LHSYNC [s: period]
Segment size × LCP0 [s: period] < LHSYNC [s: period]
SYS
/2, f
SYS
/4, f
SYS
/8, f
f
f
f
SYS
SYS
SYS
TMP92CF26A
SYS
/48
/2
/4
2007-11-21
/16, f
SYS
/24

Related parts for TMP92CF26AXBG