TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 105

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

SRS2
0
0
0
0
1
1
1
1
SDRCR<SRS2: 0>
[Hz])
(3) CPU + LDMA + ARDMA
t
CPU bus stop rate = t
STOP
display RAM but also when SDRAM is used as work, data, or stack area. The SDRAM
controller occupies the bus (ARDMA) while it refreshes SDRAM data by the auto
refresh function.
several clocks per specified number of states. However, if the LCD controller occupies
the bus continuously, ARDMA cannot be executed at normal intervals and refresh data
is stored in a counter specifically provided in the SDRAM controller. In this case,
ARDMA is executed successively after the LCD controller releases the bus.
SDRAMC > CPU. The time the CPU stops operation while the LCD controller and
SDRAM controller are transferring data for one line is defined as “t
ARDMA)”, which is calculated as follows:
SRS1
(LDMA･ARDMA) = t
The SDRAM controller owns the bus not only when SDRAM is used as the LCD
No special consideration is needed for the ARDMA time normally as it ends within
The priorities among the three bus masters should be set in the order of LCDC >
0
0
1
1
0
0
1
1
SRS0
0
1
0
1
0
1
0
1
STOP
Refresh
(states)
Interval
Auto
1248
156
312
468
624
936
(LDMA･ARDMA)[s] / LHSYNC [period: s]
47
78
Auto Refresh Intervals
STOP
92CF26A-104
(LDMA)[s] − (t
6 MHz
104.0
156.0
208.0
13.0
26.0
52.0
78.0
7.8
10MHz
124.8
15.6
31.2
46.8
62.4
93.6
4.7
7.8
STOP
Frequency (System Clock)
20MHz
(LDMA)[s] / AR interval [s] × 2 / f
15.6
23.4
31.2
46.8
62.4
2.4
3.9
7.8
40MHz
11.70
15.60
23.40
31.20
1.18
1.95
3.90
7.80
60MHz
10.40
15.60
20.80
0.78
1.30
2.60
5.20
7.80
TMP92CF26A
STOP
2007-11-21
(LDMA･
80MHz
Unit: [μs]
11.70
15.60
0.59
0.98
1.95
3.90
5.85
7.80
SYS