TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 407

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

1000: FIFO_ENABLE
1001: INIT_DESCRIPTOR
1010: FIFO_CLEA
1011: STAL_CLEAR
If FIFO is set to disable by FIFO_DISABLE COMMAND, this command is used for
release of disable condition. If set while receiving packet, this becomes valid from next
token. If USB_RESET is detected from host and RESET COMMAND execute and
transfer mode is set by using SET_CONFIG and SET_INTERFACE request, the
corresponding endpoint enters FIFO_ENABLE condition.
If UDC detects USB_RESET from host controller, it reads content of descriptor RAM
automatically, and it performs relevant settings.
If descriptor RAM is changed during system operation, it must read setting again.
Therefore, execute this command. When connected to USB host, this function starts
reading automatically. Therefore, in this case, it is not necessary to execute this
command.
However, EPx_STATUS<TOGGLE> is not initialized.
If resetting by software, execute this COMMAND.
This command Initializes the following item.
・Clear STALL of relevant endpoint.
・Set to FIFO_ENABLE condition.
This COMMAND clear STALL of corresponding endpoint (EP1 to EP3).
If clearing only STALL of endpoint, execute this COMMAND.
This COMMAND sets FIFO of corresponding endpoint to enable (EP1 to EP3).
This COMMAND is used if descriptor RAM is rewritten during system operation (EP0).
This COMMAND initializes FIFO of corresponding endpoint (EP1 to EP3).
92CF26A-406
TMP92CF26A
2007-11-21