TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 438

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

INT_SETUP
INT_ ENDPOINT0
INT_STATUS
REQUEST FLAG
DATASET register
BRD
BWR
SETUP DATA0 ACK
bmRequestType register
bRequest register
wValue register
wIndex register
wLength register
Figure 3.16.10 The Control Flow in UDC (Control Read Transfer Type)
Stage change condition of control read transfer type
These changing conditions are shown in Figure 3.16.10.
1.
2.
3.
• Start setup stage in UDC.
• Receive data in request normally and judge. And assert INT_SETUP
• Change data stage in the UDC.
• The CPU receives a request from the request register every INT_SETUP
• Judge request and access Setup Received register to inform the UDC that
• According to Device request, monitor EP0 bit of DATASET register, and write
• If the UDC is set data of payload to FIFO or CPU set short packet transfer in
• The UDC transfers data that is set to FIFO to host by IN token interrupts.
• When the CPU finishes transaction, it writes “0” to EP0 bit of EOP register.
• Change status stage in the UDC.
• Return ACK to OUT token, and change state to IDLE in the UDC.
• Assert INT_STATUS interrupt externally.
Receive SETUP token from host
Receive IN token from host
Receive OUT token from host.
interrupt externally.
interrupt.
INT_SETUP interrupt has been recognized.
data to FIFO.
EOP register, EP0 bit of DATASET register is set.
IN
NAK
Setup Received register
IN
92CF26A-437
DATA1
ACK
EP0_FIFO (WR of payload)
EP0_FIFO (Rest data)
IN
DATA0
ACK
OUT
EOP register
DATA1
TMP92CF26A
2007-11-21
ACK