TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 508

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

(i) <WLVLn>
(j) <TEMPn>
(k) <FSELn>
(l) <CLKSn>
(m) <CKn7:n0>
(n) <WSn5:n0>
<WLVLn>. Refer the “Fi/Fo buffer and data format" in details.
Before changing the data format, set <SYSCKEn>= “1”, <CNTEn>= “0” and
<TXEn>=“0”.
in details.
the data format, set <SYSCKEn>=“1”, <CNTEn>=“0” and <TXEn>=“0”.
time. In details, refer the chapter of PLL, please.
changing the counter value, set <SYSCKEn>=“1”, <CNTEn>=“0” and <TXEn>=“0”.
changing the counter value, set <SYSCKEn>=“1”, <CNTEn>=“0” and <TXEn>=“0”.
This bit controls phase of Word Select signal: I2SnWS
I2SnWS signal always out “1” level first. The order of data output changes by
It is not possible to change phase of Word Select signal during data transmission.
This bit is empty flag of output Fi/Fo buffer.
<TEMPn>=“1”: Fi/Fo buffer is empty, <TEMPn>=“0”: remain data in Fi/Fo buffer.
This bit is read only. Fi/Fo buffer is cleared by <TXEn>=“0”
This bit controls sound mode: Stereo / Monaural
<FSELn>=“0”: Stereo, <FSELn>=“1”: Monaural. Refer the chapter of “Data format”
It is not possible to change sound mode during data transmission. Before changing
This bit controls source clock to I
<CLKSn>=“0”: f
In case of using f
These bits are set counter value of clock generator. [I2SnCK]
It is not possible to change these counter value during data transmission. Before
These bits are set counter value of clock generator. [I2SnWS]
It is not possible to change these counter value during data transmission. Before
SYS
PLL
is supplied, <CLKSn>=“1”: f
, before set f
92CF26A-507
2
S circuit: f
PLL
clock, please take care set -up time: Lock-Up
SYS
/ f
PLL
PLL
is supplied.
.
TMP92CF26A
2007-11-21