TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 406

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

COMMAND
(07D0H)
3.16.3.21 COMMAND Register
bit Symbol
Read/Write
Reset State
EP [2:0] (Bit6 to bit4)
COMMAND [3:0] (Bit3 to bit0)
Note: When writing to this register, a recovery time of 3clock at 12MHz is needed. If writing continuously, insert
000: Select endpoint 0
001: Select endpoint 1
010: Select endpoint 2
011: Select endpoint 3
0000: Reserved
0001: Reserved
0010: SET_DATA0
0011: RESET
0100: STALL
0101: INVALID
0110: CREATE_SOF
0111: FIFO_DISABLE
dummy instruction of more than 250 ns.
endpoint in bit6 to bit4 and kind of COMMAND in bit3 to bit0.
This register sets COMMAND at each endpoint. This register can be set to select of
COMMAND for endpoint that is supported is ignored.
7
EP[2]
W
6
0
If this COMMAND is input, it sets toggle sequence bit of the corresponding endpoint to
“0”. Data toggle for transfer is renewed automatically by UDC. However, this
COMMAND execution is required if setting toggle sequence bit of endpoint to “0”.If
control transfer type and Isochronous transfer type, execution of this COMMAND is not
required because of hardware control.
This COMMAND resets the corresponding endpoint (EP0 to EP3).
If this COMMAND is input, the corresponding endpoint is initialized. CLEAR_FEATURE
request stalls endpoint. When this stall is cleared, execute this COMMAND. (This
command does not affect transfer mode.)
This command initializes the following.
・Clear toggle sequence bit of corresponding endpoint.
・Clear STALL of corresponding endpoint.
・Set to FIFO_ENABLE condition.
If STALL handshake must be return as answer for device request, execute this
command.
EP3).
If UDC detects USB_RESET signal from USB host, it sets all endpoints (except
endpoint 0) to prohibition using it automatically. If Config and Interface are changed by
device request, set endpoint that is not used to prohibit use.
Default is set to disable, it must be used for Isochronous transfer.
This COMMAND clear toggle sequence bit of corresponding endpoint (EP0 to EP3).
This COMMAND sets corresponding endpoint to STALL (EP0 to EP3).
This COMMAND sets condition to prohibition of use corresponding endpoint (EP1 to
This COMMAND sets quasi-SOF generation function to enable (EP0).
This COMMAND sets FIFO of corresponding endpoint to disable (EP1 to EP3).
If this command is set from external, all of transfers for corresponding endpoint return
NAK. When it is set externally while receiving packet, this becomes valid from next
token. This command does not affect the packet that is transferring.
92CF26A-405
EP[1]
W
5
0
EP[0]
W
4
0
Command[3]
W
3
0
Command[2]
W
2
0
Command[1]
TMP92CF26A
W
1
0
2007-11-21
Command[0]
W
0
0