TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 747

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

HDMACA5
HDMACB5
HDMAM5
Symbol
HDMAS5
HDMAD5
(12) DMAC (6/7)
DMA
source
address
Register5
DMA
destination
address
Register5
DMA
Transfer
count
number A
Register5
DMA
Transfer
count
number B
Register5
DMA
transfer
Mode
Register5
Name
Address
095AH
095BH
095CH
0950H
0951H
0952H
0954H
0955H
0956H
0958H
0959H
D5SA15
D5SA23
D5DA15
D5DA23
D5CA15
D5CB15
D5CA7
D5CB7
D5SA7
D5DA7
7
0
0
0
0
0
0
0
0
0
0
D5SA14
D5SA22
D5DA14
D5DA22
D5CA14
D5CB14
D5SA6
D5DA6
D5CA6
D5CB6
6
0
0
0
0
0
0
0
0
0
0
92CF26A-746
D5SA13
D5SA21
D5DA13
D5DA21
D5CA13
D5CB13
D5DA5
D5CA5
D5CB5
D5SA5
5
Destination address for DMA5 (23:16)
0
0
0
0
0
0
0
0
0
0
Destination address for DMA5 (15:8)
Destination address for DMA5 (7:0)
Source address for DMA5 (23:16)
Transfer count A for DMA5 (15:8)
Transfer count B for DMA5 (15:8)
Source address for DMA5 (15:8)
Transfer count A for DMA5 (7:0)
Transfer count B for DMA5 (7:0)
Source address for DMA5 (7:0)
100: Source/destination INC
DMA transfer mode
000: Destination INC (I/O → MEM)
001: Destination DEC (I/O → MEM)
010: Source INC (MEM → I/O)
011: Source DEC (MEM → I/O)
101: Source/destination DEC
110: Source/destination fixed
111: Reserved
D5SA12
D5SA20
D5DA12
D5DA20
D5CA12
D5CB12
D5SA4
D5DA4
D5CA4
D5CB4
D5M4
(MEM → MEM)
4
0
0
0
0
0
0
0
0
0
0
0
(MEM → MEM)
(I/O→ I/O)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
D5SA11
D5SA19
D5DA11
D5DA19
D5CA11
D5CB11
D5SA3
D5DA3
D5CA3
D5CB3
D5M3
3
0
0
0
0
0
0
0
0
0
0
0
D5SA10
D5SA18
D5DA10
D5DA18
D5CA10
D5CB10
D5SA2
D5DA2
D5CA2
D5CB2
D5M2
R/W
2
0
0
0
0
0
0
0
0
0
0
0
Transfer data size
00: 1 byte
01: 2 bytes
10: 4 bytes
11: Reserved
D5DA17
D54CA1
D5SA17
D5SA9
D5DA1
D5DA9
D5CA9
D5CB1
D5CB9
D5SA1
D5M1
1
0
0
0
0
0
0
0
0
0
0
0
TMP92CF26A
2007-11-21
D5SA16
D5DA16
D5SA0
D5SA8
D5DA0
D5DA8
D5CA0
D5CA8
D5CB0
D5CB8
D5M0
0
0
0
0
0
0
0
0
0
0
0
0