TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 3

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

(4) External memory expansion
(5) Memory controller
(6) 8-bit timers: 8 channels
(7) 16-bit timer/event counter: 2 channels
(8) General-purpose serial interface: 1 channel
(9) Serial bus interface: 1 channel
(10) USB (universal serial bus) controller: 1 channel
(11) I
(12) LCD controller
(13) SDRAM controller: 1 channel
(14) Timer for real-time clock (RTC)
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2
other functions)
S (Inter-IC Sound)interface: 2 channels
UART/synchronous mode
IrDA ver.1.0 (115.2 kbps) selectable
Endpoint 1: BULK (output) 64 bytes × 2 FIFOs
Endpoint 2: BULK (input) 64 bytes × 2 FIFOs
Endpoint 3: Interrupt (input) 8 bytes × 1 FIFO
Expandable up to 3.1 Gbytes (shared program/data area)
Can simultaneously support 8-and 16-bit width external data buses
Separate bus system
Chip select output: 4 channels
One channel in 4 channels is enabled detailed AC enable setting
I
Supports USB (ver.1.1)
Full-speed (12 Mbps) (Low-speed is not supported.)
Endpoint 0: Control 64 bytes × 1 FIFO
Descriptor RAM: 384 bytes
I
Data Format is supported Left/Right Justify
128-byte FIFO buffer (64 bytes × 2) per channel
Supports monochrome, 4, 16 and 64 gray levels and 256/4096/65536 colors for STN
Supports 4096/65536/262144/16777216 colors for TFT
Supports PIP (Picture In Picture Display)
Supports H/W Rotation function for support to various LCDM
Supports 16-Mbit, 64-Mbit, 128-Mbit, 256-Mbit and 512-Mbit SDR (Single-data-rate)
Possible to execute instruction on SDRAM
Based on TC8521A
…… Dynamic data bus sizing
SDRAM
2
2
C bus mode only
S bus mode selectable (Master, transmission only)
(There is the restriction in the setting baud rate when use this function together
92CF26A-2
TMP92CF26A
2007-11-21