TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 380

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

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INT_STASN (Bit4)
INT_EPxN (Bit3, 2, 1)
This is the flag register for INT_STASN (change host status stage - interrupt).
This is set to “1” when the USB host changes to status stage at the Control read
transfer. This interrupt is needed if data length is less than wLength (specified
by the host).
But if the USB host changes to status stage, this interrupt is always generated
because this signal is designed by using NAK of the first packet. So, use mask
register USBINTMRn to avoid this interrupt always being generated. Mask this
interrupt before data of the last payload is written.
This is the flag register for INT_EPxN (NAK acknowledge to the USB host -
interrupt).
This is set to “1” when the Endpoint1, 2 and 3 transmit NAK.
92CF26A-379
TMP92CF26A
2007-11-21