TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 252

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

(i)
(k) <SPLW1:0>
(j)
this bit should be set to “0”.
an ECC calculator. The latter is used to calculate the error address and error bit position.
generated from the ECC for written data and the ECC for read data. At this time, no special
care is needed if ECC generation and error calculation are performed serially. If these
operations need to be performed parallely, the intermediate code used for error calculation
must be latched while the calculation is being performed. The <RSECCL> bit is provided to
enable this latch operation.
generator can generate the ECC for another page without problem while the ECC
calculator is calculating the error address and error bit position. At this time, the ECC
generator can perform both encode (write) and decode (read) operations.
width to be inserted is obtained by multiplying the value set in these bits by f
calculator are updated as the data in the ECC generator is updated.
Flow of data
width to be inserted is obtained by multiplying the value set in these bits by f
When <RSECCL> is set to “0”, the latch is released and the contents of the ECC
These bits are used to specify the High width of the
The <RSECCL> bit is used only for Reed-Solomon codes. When using Hamming codes,
The Reed-Solomon processing unit is comprised of two elements: an ECC generator and
The error address and error bit position are calculated using an intermediate code
When <RSECCL> is set to “1”, the intermediate code is latched so that the ECC
The <SPHW1:0> bits are used for both Hamming and Reed-Solomon codes.
The <SPLW1:0> bits are used for both Hamming and Reed-Solomon codes.
These bits are used to specify the Low width of the
<RSECCL>
<SPHW1:0>
Reed-Solomon
Reed-Solomon
Generator
Calculator
F/F 80bit
ECC
ECC
92CF26A-251
<RSECCL>=0 Latch_OFF
<RSECCL>=1 Latch_ON
NDECCRDn
Register
NDRE
NDRE
and
and
NDWE
NDWE
signals. The High
signals. The Low
TMP92CF26A
SYS.
2007-11-21
SYS.